44 	uintptr_t reg_base = imx_usdhc_params.reg_base;  in imx_usdhc_set_clk()  local
58 	mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);  in imx_usdhc_set_clk()
59 	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);  in imx_usdhc_set_clk()
62 	mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN);  in imx_usdhc_set_clk()
68 	uintptr_t reg_base = imx_usdhc_params.reg_base;  in imx_usdhc_initialize()  local
70 	assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0);  in imx_usdhc_initialize()
73 	mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA);  in imx_usdhc_initialize()
76 	while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) {  in imx_usdhc_initialize()
82 	mmio_write_32(reg_base + MMCBOOT, 0);  in imx_usdhc_initialize()
83 	mmio_write_32(reg_base + MIXCTRL, 0);  in imx_usdhc_initialize()
84 	mmio_write_32(reg_base + CLKTUNECTRLSTS, 0);  in imx_usdhc_initialize()
86 	mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT);  in imx_usdhc_initialize()
87 	mmio_write_32(reg_base + DLLCTRL, 0);  in imx_usdhc_initialize()
88 	mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN);  in imx_usdhc_initialize()
95 	mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR);  in imx_usdhc_initialize()
98 	mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE);  in imx_usdhc_initialize()
101 	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK,  in imx_usdhc_initialize()
105 	mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16));  in imx_usdhc_initialize()
112 	uintptr_t reg_base = imx_usdhc_params.reg_base;  in imx_usdhc_send_cmd()  local
120 	mmio_write_32(reg_base + INTSTAT, 0xffffffff);  in imx_usdhc_send_cmd()
124 		state = mmio_read_32(reg_base + PSTATE);  in imx_usdhc_send_cmd()
127 	while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA)  in imx_usdhc_send_cmd()
130 	mmio_write_32(reg_base + INTSIGEN, 0);  in imx_usdhc_send_cmd()
183 	mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);  in imx_usdhc_send_cmd()
184 	mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl);  in imx_usdhc_send_cmd()
185 	mmio_write_32(reg_base + XFERTYPE, xfertype);  in imx_usdhc_send_cmd()
189 		state = mmio_read_32(reg_base + INTSTAT);  in imx_usdhc_send_cmd()
208 		cmdrsp3 = mmio_read_32(reg_base + CMDRSP3);  in imx_usdhc_send_cmd()
209 		cmdrsp2 = mmio_read_32(reg_base + CMDRSP2);  in imx_usdhc_send_cmd()
210 		cmdrsp1 = mmio_read_32(reg_base + CMDRSP1);  in imx_usdhc_send_cmd()
211 		cmdrsp0 = mmio_read_32(reg_base + CMDRSP0);  in imx_usdhc_send_cmd()
217 		cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0);  in imx_usdhc_send_cmd()
224 			state = mmio_read_32(reg_base + INTSTAT);  in imx_usdhc_send_cmd()
237 		mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC);  in imx_usdhc_send_cmd()
238 		while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC)  in imx_usdhc_send_cmd()
242 			mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD);  in imx_usdhc_send_cmd()
243 			while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD)  in imx_usdhc_send_cmd()
249 	mmio_write_32(reg_base + INTSTAT, 0xffffffff);  in imx_usdhc_send_cmd()
256 	uintptr_t reg_base = imx_usdhc_params.reg_base;  in imx_usdhc_set_ios()  local
261 		mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,  in imx_usdhc_set_ios()
264 		mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,  in imx_usdhc_set_ios()
272 	uintptr_t reg_base = imx_usdhc_params.reg_base;  in imx_usdhc_prepare()  local
274 	mmio_write_32(reg_base + DSADDR, buf);  in imx_usdhc_prepare()
275 	mmio_write_32(reg_base + BLKATT,  in imx_usdhc_prepare()
295 	       ((params->reg_base & MMC_BLOCK_MASK) == 0) &&  in imx_usdhc_init()