Lines Matching refs:priv
31 struct bcmspi_priv *priv = NULL; in iproc_qspi_setup() local
34 priv = &spi_cfg; in iproc_qspi_setup()
35 priv->spi_mode = mode; in iproc_qspi_setup()
36 priv->state = QSPI_STATE_DISABLED; in iproc_qspi_setup()
37 priv->bspi_hw = QSPI_BSPI_MODE_REG_BASE; in iproc_qspi_setup()
38 priv->mspi_hw = QSPI_MSPI_MODE_REG_BASE; in iproc_qspi_setup()
44 priv->max_hz = max_hz; in iproc_qspi_setup()
47 mmio_write_32(priv->mspi_hw + MSPI_SPCR1_LSB_REG, 0); in iproc_qspi_setup()
48 mmio_write_32(priv->mspi_hw + MSPI_SPCR1_MSB_REG, 0); in iproc_qspi_setup()
49 mmio_write_32(priv->mspi_hw + MSPI_NEWQP_REG, 0); in iproc_qspi_setup()
50 mmio_write_32(priv->mspi_hw + MSPI_ENDQP_REG, 0); in iproc_qspi_setup()
51 mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG, 0); in iproc_qspi_setup()
54 spbr = (QSPI_AXI_CLK - 1) / (2 * priv->max_hz) + 1; in iproc_qspi_setup()
57 mmio_write_32(priv->mspi_hw + MSPI_SPCR0_LSB_REG, spbr); in iproc_qspi_setup()
60 priv->mspi_16bit = 0; in iproc_qspi_setup()
61 mmio_write_32(priv->mspi_hw + MSPI_SPCR0_MSB_REG, in iproc_qspi_setup()
64 (priv->spi_mode & MSPI_SPCR0_MSB_REG_MODE_MASK)); /* mode: CPOL / CPHA */ in iproc_qspi_setup()
68 mmio_read_32(priv->mspi_hw + MSPI_SPCR0_LSB_REG)); in iproc_qspi_setup()
70 mmio_read_32(priv->mspi_hw + MSPI_SPCR0_MSB_REG)); in iproc_qspi_setup()
72 mmio_read_32(priv->mspi_hw + MSPI_SPCR1_LSB_REG)); in iproc_qspi_setup()
74 mmio_read_32(priv->mspi_hw + MSPI_SPCR1_MSB_REG)); in iproc_qspi_setup()
76 mmio_read_32(priv->mspi_hw + MSPI_SPCR2_REG)); in iproc_qspi_setup()
77 VERBOSE("SPI: CLK: %d\n", priv->max_hz); in iproc_qspi_setup()
82 void bcmspi_enable_bspi(struct bcmspi_priv *priv) in bcmspi_enable_bspi() argument
84 if (priv->state != QSPI_STATE_BSPI) { in bcmspi_enable_bspi()
86 mmio_write_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG, 0); in bcmspi_enable_bspi()
88 priv->state = QSPI_STATE_BSPI; in bcmspi_enable_bspi()
92 static int bcmspi_disable_bspi(struct bcmspi_priv *priv) in bcmspi_disable_bspi() argument
96 if (priv->state == QSPI_STATE_MSPI) in bcmspi_disable_bspi()
100 if ((mmio_read_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) & in bcmspi_disable_bspi()
105 priv->bspi_hw + BSPI_BUSY_STATUS_REG) & in bcmspi_disable_bspi()
107 mmio_write_32(priv->bspi_hw + in bcmspi_disable_bspi()
116 if ((mmio_read_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) & in bcmspi_disable_bspi()
124 priv->state = QSPI_STATE_MSPI; in bcmspi_disable_bspi()
131 struct bcmspi_priv *priv = &spi_cfg; in iproc_qspi_claim_bus() local
134 if (bcmspi_disable_bspi(priv) != 0) in iproc_qspi_claim_bus()
142 struct bcmspi_priv *priv = &spi_cfg; in iproc_qspi_release_bus() local
145 bcmspi_enable_bspi(priv); in iproc_qspi_release_bus()
148 static int mspi_xfer(struct bcmspi_priv *priv, uint32_t bytes, in mspi_xfer() argument
166 priv->mspi_16bit = 0; in mspi_xfer()
168 priv->mspi_16bit = 1; in mspi_xfer()
178 if (priv->mspi_16bit) { in mspi_xfer()
187 mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG + in mspi_xfer()
193 mmio_write_32(priv->mspi_hw + in mspi_xfer()
205 mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG + in mspi_xfer()
208 mmio_write_32(priv->mspi_hw + in mspi_xfer()
219 mmio_write_32(priv->mspi_hw + MSPI_NEWQP_REG, 0); in mspi_xfer()
220 mmio_write_32(priv->mspi_hw + MSPI_ENDQP_REG, queues - 1); in mspi_xfer()
224 mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG + in mspi_xfer()
228 mmio_write_32(priv->mspi_hw + MSPI_STATUS_REG, 0); in mspi_xfer()
230 mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG, MSPI_SPE); in mspi_xfer()
232 mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG, in mspi_xfer()
238 if (mmio_read_32(priv->mspi_hw + MSPI_STATUS_REG) & in mspi_xfer()
244 if ((mmio_read_32(priv->mspi_hw + MSPI_STATUS_REG) & in mspi_xfer()
252 if (priv->mspi_16bit) { in mspi_xfer()
254 rx[i] = mmio_read_32(priv->mspi_hw + in mspi_xfer()
261 rx[i] = mmio_read_32(priv->mspi_hw + in mspi_xfer()
277 struct bcmspi_priv *priv; in iproc_qspi_xfer() local
283 priv = &spi_cfg; in iproc_qspi_xfer()
285 if (priv->state == QSPI_STATE_DISABLED) { in iproc_qspi_xfer()
300 if (bcmspi_disable_bspi(priv) != 0) { in iproc_qspi_xfer()
305 mmio_write_32(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 1); in iproc_qspi_xfer()
310 ret = mspi_xfer(priv, bytes, tx, rx, flags); in iproc_qspi_xfer()
314 mmio_write_32(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 0); in iproc_qspi_xfer()