Lines Matching refs:in
5 operations in the Trusted Firmware-A Power State Coordination Interface (PSCI)
6 implementation, using the in-built Performance Measurement Framework (PMF) and
75 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
94 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
113 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
132 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
154 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
173 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
192 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
210 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
231 ``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
272 ``CPU_VERSION`` in parallel
275 .. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.9)
293 .. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.10)
315 TF-A was built using the same build instructions as detailed in the procedure
318 In the results below, CPUs 0-3 refer to CPUs in the little cluster (A53) and
319 CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead
325 ``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
344 A large variance in ``PSCI_ENTRY`` and ``PSCI_EXIT`` times across CPUs is
346 for the 3 other CPUs in the cluster (0-2) to complete ``PSCI_ENTRY`` and release
350 last CPUs in their respective clusters to power down, therefore both the L1 and
357 ``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
376 There is no lock contention in TF generic code at power level 0 but the large
377 variance in ``PSCI_ENTRY`` times across CPUs is due to lock contention in Juno
392 ``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
411 The ``CFLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster
412 are large because all other CPUs in the cluster are powered down during the
424 ``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
447 The ``PSCI_ENTRY`` times for CPUs in the big cluster are slightly smaller than
448 for the CPUs in little cluster due to greater CPU performance.
450 The ``PSCI_EXIT`` times are generally lower than in the last test because the
454 ``CPU_OFF`` on all non-lead CPUs in sequence then ``CPU_SUSPEND`` on lead CPU to deepest power level
459 1. Call ``CPU_ON`` and ``CPU_OFF`` on each non-lead CPU in sequence.
482 CPUs in that cluster are powerered down during the test. The ``CPU_OFF`` call
493 The ``PSCI_EXIT`` times for CPUs in the big cluster are slightly smaller than
494 for CPUs in the little cluster due to greater CPU performance. These times
495 generally are greater than the ``PSCI_EXIT`` times in the ``CPU_SUSPEND`` tests
496 because there is more code to execute in the "on finisher" compared to the
499 ``PSCI_VERSION`` on all CPUs in parallel
503 approximates the round trip latency for handling a fast SMC at EL3 in TF.