Lines Matching refs:structure
115 - BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
116 structure contains the memory layout available to BL2.
282 contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the
622 pass a ``bl31_params`` structure.
634 TF-A's BL2 implementation passes a ``bl31_params`` structure in
651 BL2, a platform that uses an extended entry_point_info structure to convey
662 uint8_t type; /* type of the structure */
663 uint8_t version; /* version of this structure */
664 uint16_t size; /* size of this structure in bytes */
733 evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
744 ``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
758 of ``bl31_params``. The ``bl_params`` structure is based on the convention
850 This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling
1078 which returns a reference to the ``entry_point_info`` structure corresponding to
1395 The CPU specific operations framework depends on the ``cpu_ops`` structure which
1401 The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
2178 The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2180 structure is allocated in the coherent memory region in TF-A because it can be
2212 In order to move this data structure to normal memory, the use of each of its
2226 The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2246 ``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2256 CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2261 To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2263 algorithm mentioned earlier. The bakery_lock structure only allocates the memory
2268 perform software cache maintenance on the lock data structure without running
2271 The bakery lock data structure ``bakery_info_t`` is defined for use when
2671 PMF code structure