Lines Matching refs:CTX_EL3STATE_OFFSET
114 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
116 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
118 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
120 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
123 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG]
140 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
142 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
143 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
145 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
146 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
148 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
156 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
157 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
249 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
257 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
265 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
281 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
307 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
312 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
322 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]