Lines Matching refs:ddr_data
102 static struct px30_sleep_ddr_data ddr_data variable
184 SAVE_QOS(ddr_data.cpu_qos, CPU); in qos_save()
187 SAVE_QOS(ddr_data.gpu_qos, GPU); in qos_save()
189 SAVE_QOS(ddr_data.isp_128m_qos, ISP_128M); in qos_save()
190 SAVE_QOS(ddr_data.isp_rd_qos, ISP_RD); in qos_save()
191 SAVE_QOS(ddr_data.isp_wr_qos, ISP_WR); in qos_save()
192 SAVE_QOS(ddr_data.isp_m1_qos, ISP_M1); in qos_save()
193 SAVE_QOS(ddr_data.vip_qos, VIP); in qos_save()
196 SAVE_QOS(ddr_data.rga_rd_qos, RGA_RD); in qos_save()
197 SAVE_QOS(ddr_data.rga_wr_qos, RGA_WR); in qos_save()
198 SAVE_QOS(ddr_data.vop_m0_qos, VOP_M0); in qos_save()
199 SAVE_QOS(ddr_data.vop_m1_qos, VOP_M1); in qos_save()
202 SAVE_QOS(ddr_data.vpu_qos, VPU); in qos_save()
203 SAVE_QOS(ddr_data.vpu_r128_qos, VPU_R128); in qos_save()
206 SAVE_QOS(ddr_data.emmc_qos, EMMC); in qos_save()
207 SAVE_QOS(ddr_data.nand_qos, NAND); in qos_save()
208 SAVE_QOS(ddr_data.sdio_qos, SDIO); in qos_save()
209 SAVE_QOS(ddr_data.sfc_qos, SFC); in qos_save()
212 SAVE_QOS(ddr_data.gmac_qos, GMAC); in qos_save()
214 SAVE_QOS(ddr_data.crypto_qos, CRYPTO); in qos_save()
216 SAVE_QOS(ddr_data.sdmmc_qos, SDMMC); in qos_save()
218 SAVE_QOS(ddr_data.usb_host_qos, USB_HOST); in qos_save()
219 SAVE_QOS(ddr_data.usb_otg_qos, USB_OTG); in qos_save()
225 RESTORE_QOS(ddr_data.cpu_qos, CPU); in qos_restore()
228 RESTORE_QOS(ddr_data.gpu_qos, GPU); in qos_restore()
230 RESTORE_QOS(ddr_data.isp_128m_qos, ISP_128M); in qos_restore()
231 RESTORE_QOS(ddr_data.isp_rd_qos, ISP_RD); in qos_restore()
232 RESTORE_QOS(ddr_data.isp_wr_qos, ISP_WR); in qos_restore()
233 RESTORE_QOS(ddr_data.isp_m1_qos, ISP_M1); in qos_restore()
234 RESTORE_QOS(ddr_data.vip_qos, VIP); in qos_restore()
237 RESTORE_QOS(ddr_data.rga_rd_qos, RGA_RD); in qos_restore()
238 RESTORE_QOS(ddr_data.rga_wr_qos, RGA_WR); in qos_restore()
239 RESTORE_QOS(ddr_data.vop_m0_qos, VOP_M0); in qos_restore()
240 RESTORE_QOS(ddr_data.vop_m1_qos, VOP_M1); in qos_restore()
243 RESTORE_QOS(ddr_data.vpu_qos, VPU); in qos_restore()
244 RESTORE_QOS(ddr_data.vpu_r128_qos, VPU_R128); in qos_restore()
247 RESTORE_QOS(ddr_data.emmc_qos, EMMC); in qos_restore()
248 RESTORE_QOS(ddr_data.nand_qos, NAND); in qos_restore()
249 RESTORE_QOS(ddr_data.sdio_qos, SDIO); in qos_restore()
250 RESTORE_QOS(ddr_data.sfc_qos, SFC); in qos_restore()
253 RESTORE_QOS(ddr_data.gmac_qos, GMAC); in qos_restore()
255 RESTORE_QOS(ddr_data.crypto_qos, CRYPTO); in qos_restore()
257 RESTORE_QOS(ddr_data.sdmmc_qos, SDMMC); in qos_restore()
259 RESTORE_QOS(ddr_data.usb_host_qos, USB_HOST); in qos_restore()
260 RESTORE_QOS(ddr_data.usb_otg_qos, USB_OTG); in qos_restore()
549 ddr_data.cru_clk_gate[i] = in clk_gate_suspend()
556 ddr_data.cru_pmu_clk_gate[i] = in clk_gate_suspend()
569 WITH_16BITS_WMSK(ddr_data.cru_pmu_clk_gate[i])); in clk_gate_resume()
573 WITH_16BITS_WMSK(ddr_data.cru_clk_gate[i])); in clk_gate_resume()
580 ddr_data.pmu_cru_clksel_con0 = in pvtm_32k_config()
583 ddr_data.pgrf_pvtm_con[0] = in pvtm_32k_config()
585 ddr_data.pgrf_pvtm_con[1] = in pvtm_32k_config()
636 ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14)); in pvtm_32k_config_restore()
639 WITH_16BITS_WMSK(ddr_data.pgrf_pvtm_con[0])); in pvtm_32k_config_restore()
641 ddr_data.pgrf_pvtm_con[1]); in pvtm_32k_config_restore()
647 ddr_data.ddrc_pwrctrl = mmio_read_32(DDR_UPCTL_BASE + 0x30); in ddr_sleep_config()
651 ddr_data.ddrgrf_con1 = mmio_read_32(DDRGRF_BASE + 0x4); in ddr_sleep_config()
655 ddr_data.ddrstdby_con0 = mmio_read_32(DDR_STDBY_BASE + 0x0); in ddr_sleep_config()
661 ddr_data.ddrgrf_con0 = mmio_read_32(DDRGRF_BASE + 0x0); in ddr_sleep_config()
667 ddr_data.pmugrf_soc_con0 = in ddr_sleep_config()
677 ddr_data.pmugrf_soc_con0 | BITS_WMSK(0x1, 12)); in ddr_sleep_config_restore()
681 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 4)); in ddr_sleep_config_restore()
684 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 5)); in ddr_sleep_config_restore()
688 ddr_data.ddrstdby_con0 | BITS_WMSK(0x1, 0)); in ddr_sleep_config_restore()
692 ddr_data.ddrgrf_con1 | BITS_WMSK(0x1f, 0)); in ddr_sleep_config_restore()
696 ddr_data.ddrc_pwrctrl | BITS_WMSK(0x3, 0)); in ddr_sleep_config_restore()
706 ddr_data.pmic_slp_iomux = mmio_read_32(PMUGRF_BASE + GPIO0A_IOMUX); in pmu_sleep_config()
708 ddr_data.pmu_pwrmd_core_l = in pmu_sleep_config()
710 ddr_data.pmu_pwrmd_core_h = in pmu_sleep_config()
712 ddr_data.pmu_pwrmd_cmm_l = in pmu_sleep_config()
714 ddr_data.pmu_pwrmd_cmm_h = in pmu_sleep_config()
716 ddr_data.pmu_wkup_cfg2_l = mmio_read_32(PMU_BASE + PMU_WKUP_CFG2_LO); in pmu_sleep_config()
815 WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_core_l)); in pmu_sleep_restore()
817 WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_core_h)); in pmu_sleep_restore()
819 WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_cmm_l)); in pmu_sleep_restore()
821 WITH_16BITS_WMSK(ddr_data.pmu_pwrmd_cmm_h)); in pmu_sleep_restore()
823 WITH_16BITS_WMSK(ddr_data.pmu_wkup_cfg2_l)); in pmu_sleep_restore()
827 WITH_16BITS_WMSK(ddr_data.pmic_slp_iomux)); in pmu_sleep_restore()
832 ddr_data.gpio0c_iomux = mmio_read_32(PMUGRF_BASE + GPIO0C_IOMUX); in soc_sleep_config()
852 WITH_16BITS_WMSK(ddr_data.gpio0c_iomux)); in soc_sleep_restore()
905 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
918 mode = (ddr_data.cru_mode_save >> PLL_MODE_SHIFT(pll_id)) & 0x3; in pll_resume()
921 mode = ddr_data.cru_pmu_mode_save & 0x3; in pll_resume()
925 if (ddr_data.cru_plls_con_save[pll_id][1] & PLL_LOCK_MSK) in pll_resume()
933 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_MODE); in pm_plls_suspend()
934 ddr_data.cru_pmu_mode_save = mmio_read_32(PMUCRU_BASE + CRU_PMU_MODE); in pm_plls_suspend()
935 ddr_data.clk_sel0 = mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(0)); in pm_plls_suspend()
955 ddr_data.clk_sel0 | BITS_WMSK(0xf, 8)); in pm_plls_resume()
959 ddr_data.clk_sel0 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
1057 psram_boot_cfg->ddr_data = (uint64_t)0; in plat_rockchip_pmu_init()