Lines Matching refs:sp
383 ldr x17, [sp, #CTX_EL3STATE_OFFSET + CTX_MPAM3_EL3]
405 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
406 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
407 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
408 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
409 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
410 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
411 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
412 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
413 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
414 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
415 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
416 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
417 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
418 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
419 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
421 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
425 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
436 add x19, sp, #CTX_PAUTH_REGS_OFFSET
488 add x10, sp, #CTX_PAUTH_REGS_OFFSET
509 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
511 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
512 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
513 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
514 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
515 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
516 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
517 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
518 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
519 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
520 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
521 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
522 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
523 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
524 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
525 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
527 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
542 str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1)]
544 str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_TCR_EL1)]
582 ldr x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
612 mov x17, sp
614 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
646 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE]
660 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
661 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
675 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
679 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG]