Lines Matching full:1
10 * 1. Redistributions of source code must retain the above copyright
58 #define UART_DATA_READY (1 << 0)
59 #define UART_TRANSMIT_SHIFT_EMPTY (1 << 1)
60 #define UART_TRANSMIT_FIFO_EMPTY (1 << 2)
61 #define UART_BREAK_RECEIVED (1 << 3)
62 #define UART_OVERRUN (1 << 4)
63 #define UART_PARITY_ERROR (1 << 5)
64 #define UART_FRAMING_ERROR (1 << 6)
65 #define UART_TRANSMIT_FIFO_HALF (1 << 7)
66 #define UART_RECEIVE_FIFO_HALF (1 << 8)
67 #define UART_TRANSMIT_FIFO_FULL (1 << 9)
68 #define UART_RECEIVE_FIFO_FULL (1 << 10)
71 #define UART_RECEIVE_ENABLE (1 << 0)
72 #define UART_TRANSMIT_ENABLE (1 << 1)
73 #define UART_RECEIVE_INTERRUPT (1 << 2)
74 #define UART_TRANSMIT_INTERRUPT (1 << 3)
75 #define UART_PARITY_SELECT (1 << 4)
76 #define UART_PARITY_ENABLE (1 << 5)
77 #define UART_FLOW_CONTROL (1 << 6)
78 #define UART_LOOPBACK (1 << 7)
79 #define UART_EXTERNAL_CLOCK (1 << 8)
80 #define UART_RECEIVE_FIFO_INTERRUPT (1 << 9)
81 #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
82 #define UART_FIFO_DEBUG_MODE (1 << 11)
83 #define UART_OUTPUT_ENABLE (1 << 12)
84 #define UART_FIFO_AVAILABLE (1 << 31)