Lines Matching +full:runs +full:- +full:on
2 * SPDX-License-Identifier: BSD-3-Clause
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
42 * Cortex-mM includes an NVIC and starts with SP initialized, so start
60 * MVE is used. This is described in "Arm v8-M Architecture Reference in _start()
73 * a valid value for 8.1-m low overhead loops. */ in _start()
104 * which runs from 0x00000000 to 0x7fffffff along with the usual
105 * Device space which runs from 0x80000000 to 0xffffffff.
111 /* Bits within a short-form section PTE (1MB mapping) */
212 * Regular ARM has an 8-entry exception vector and starts without SP
329 unsigned digitval = 0xF & (reg >> (28 - 4*i)); in arm_fault_write_reg()
330 char digitchr = '0' + digitval + (digitval >= 10 ? 'a'-'0'-10 : 0); in arm_fault_write_reg()
369 arm_fault_write_reg("\tR0: 0x", f->r0); in arm_fault()
370 arm_fault_write_reg("\tR1: 0x", f->r1); in arm_fault()
371 arm_fault_write_reg("\tR2: 0x", f->r2); in arm_fault()
372 arm_fault_write_reg("\tR3: 0x", f->r3); in arm_fault()
373 arm_fault_write_reg("\tR12: 0x", f->r12); in arm_fault()
374 arm_fault_write_reg("\tLR: 0x", f->lr); in arm_fault()
375 arm_fault_write_reg("\tPC: 0x", f->pc); in arm_fault()
376 arm_fault_write_reg("\tXPSR: 0x", f->xpsr); in arm_fault()
440 arm_fault_write_reg(prefix, f->r[r]); in arm_fault()
442 arm_fault_write_reg("\tPC: 0x", f->pc); in arm_fault()
448 __asm__("push {r0-r6}"); \