Lines Matching refs:a1
294 PTR_SUBU t0,a0,a1
325 xor t8,a1,a0
334 C_LDHI t8,0(a1)
335 PTR_ADDU a1,a1,a3
360 lb a3, 6(a1)
363 lb a3, 5(a1)
366 lb a3, 4(a1)
369 lb a3, 3(a1)
372 lb a3, 2(a1)
375 lb a3, 1(a1)
378 lb a3, 0(a1)
385 PTR_ADDU a1,a1,t8
388 andi t8,a1,(NSIZE-1)
430 PREFETCH_FOR_LOAD (0, a1)
431 PREFETCH_FOR_LOAD (1, a1)
432 PREFETCH_FOR_LOAD (2, a1)
433 PREFETCH_FOR_LOAD (3, a1)
458 C_LD t0,UNIT(0)(a1)
463 C_LD t1,UNIT(1)(a1)
477 C_LD REG2,UNIT(2)(a1)
478 C_LD REG3,UNIT(3)(a1)
479 C_LD REG4,UNIT(4)(a1)
480 C_LD REG5,UNIT(5)(a1)
481 C_LD REG6,UNIT(6)(a1)
482 C_LD REG7,UNIT(7)(a1)
484 PREFETCH_FOR_LOAD (4, a1)
486 PREFETCH_FOR_LOAD (3, a1)
497 C_LD t0,UNIT(8)(a1)
498 C_LD t1,UNIT(9)(a1)
499 C_LD REG2,UNIT(10)(a1)
500 C_LD REG3,UNIT(11)(a1)
501 C_LD REG4,UNIT(12)(a1)
502 C_LD REG5,UNIT(13)(a1)
503 C_LD REG6,UNIT(14)(a1)
504 C_LD REG7,UNIT(15)(a1)
506 PREFETCH_FOR_LOAD (5, a1)
518 PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
528 PREFETCH_FOR_LOAD (0, a1)
533 C_LD t0,UNIT(0)(a1)
534 C_LD t1,UNIT(1)(a1)
535 C_LD REG2,UNIT(2)(a1)
536 C_LD REG3,UNIT(3)(a1)
537 C_LD REG4,UNIT(4)(a1)
538 C_LD REG5,UNIT(5)(a1)
539 C_LD REG6,UNIT(6)(a1)
540 C_LD REG7,UNIT(7)(a1)
541 PTR_ADDIU a1,a1,UNIT(8)
567 C_LD REG3,UNIT(0)(a1)
569 PTR_ADDIU a1,a1,UNIT(1)
581 lw REG3,0(a1)
584 PTR_ADDIU a1,a1,4
592 lb v1,0(a1)
594 PTR_ADDIU a1,a1,1
612 andi t9,a1,3
619 lw REG3,0(a1)
621 PTR_ADDIU a1,a1,4
643 C_LDHI v1,UNIT(0)(a1)
644 C_LDLO v1,UNITM1(1)(a1)
645 PTR_ADDU a1,a1,a3
667 PREFETCH_FOR_LOAD (0, a1)
668 PREFETCH_FOR_LOAD (1, a1)
669 PREFETCH_FOR_LOAD (2, a1)
687 PREFETCH_FOR_LOAD (3, a1)
688 C_LDHI t0,UNIT(0)(a1)
689 C_LDHI t1,UNIT(1)(a1)
690 C_LDHI REG2,UNIT(2)(a1)
695 C_LDHI REG3,UNIT(3)(a1)
699 C_LDHI REG4,UNIT(4)(a1)
700 C_LDHI REG5,UNIT(5)(a1)
701 C_LDHI REG6,UNIT(6)(a1)
702 C_LDHI REG7,UNIT(7)(a1)
703 C_LDLO t0,UNITM1(1)(a1)
704 C_LDLO t1,UNITM1(2)(a1)
705 C_LDLO REG2,UNITM1(3)(a1)
706 C_LDLO REG3,UNITM1(4)(a1)
707 C_LDLO REG4,UNITM1(5)(a1)
708 C_LDLO REG5,UNITM1(6)(a1)
709 C_LDLO REG6,UNITM1(7)(a1)
710 C_LDLO REG7,UNITM1(8)(a1)
711 PREFETCH_FOR_LOAD (4, a1)
720 C_LDHI t0,UNIT(8)(a1)
721 C_LDHI t1,UNIT(9)(a1)
722 C_LDHI REG2,UNIT(10)(a1)
723 C_LDHI REG3,UNIT(11)(a1)
724 C_LDHI REG4,UNIT(12)(a1)
725 C_LDHI REG5,UNIT(13)(a1)
726 C_LDHI REG6,UNIT(14)(a1)
727 C_LDHI REG7,UNIT(15)(a1)
728 C_LDLO t0,UNITM1(9)(a1)
729 C_LDLO t1,UNITM1(10)(a1)
730 C_LDLO REG2,UNITM1(11)(a1)
731 C_LDLO REG3,UNITM1(12)(a1)
732 C_LDLO REG4,UNITM1(13)(a1)
733 C_LDLO REG5,UNITM1(14)(a1)
734 C_LDLO REG6,UNITM1(15)(a1)
735 C_LDLO REG7,UNITM1(16)(a1)
736 PREFETCH_FOR_LOAD (5, a1)
747 PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
756 PREFETCH_FOR_LOAD (0, a1)
761 C_LDHI t0,UNIT(0)(a1)
762 C_LDHI t1,UNIT(1)(a1)
763 C_LDHI REG2,UNIT(2)(a1)
764 C_LDHI REG3,UNIT(3)(a1)
765 C_LDHI REG4,UNIT(4)(a1)
766 C_LDHI REG5,UNIT(5)(a1)
767 C_LDHI REG6,UNIT(6)(a1)
768 C_LDHI REG7,UNIT(7)(a1)
769 C_LDLO t0,UNITM1(1)(a1)
770 C_LDLO t1,UNITM1(2)(a1)
771 C_LDLO REG2,UNITM1(3)(a1)
772 C_LDLO REG3,UNITM1(4)(a1)
773 C_LDLO REG4,UNITM1(5)(a1)
774 C_LDLO REG5,UNITM1(6)(a1)
775 C_LDLO REG6,UNITM1(7)(a1)
776 C_LDLO REG7,UNITM1(8)(a1)
777 PTR_ADDIU a1,a1,UNIT(8)
799 C_LDHI v1,UNIT(0)(a1)
800 C_LDLO v1,UNITM1(1)(a1)
802 PTR_ADDIU a1,a1,UNIT(1)
811 lb v1,0(a1)
813 PTR_ADDIU a1,a1,1
837 PTR_SUBU REG2, a1, t8; /* REG2 is the aligned src address. */ \
838 PTR_ADDU a1, a1, a3; /* a1 is addr of source after word loop. */ \