Lines Matching refs:a0
294 PTR_SUBU t0,a0,a1
314 move v0,a0
325 xor t8,a1,a0
328 PTR_SUBU a3, zero, a0
336 C_STHI t8,0(a0)
337 PTR_ADDU a0,a0,a3
346 andi t8,a0,7
361 sb a3, 6(a0)
364 sb a3, 5(a0)
367 sb a3, 4(a0)
370 sb a3, 3(a0)
373 sb a3, 2(a0)
376 sb a3, 1(a0)
379 sb a3, 0(a0)
384 PTR_ADDU a0,a0,t8
418 PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
427 PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
435 PREFETCH_FOR_STORE (1, a0)
436 PREFETCH_FOR_STORE (2, a0)
437 PREFETCH_FOR_STORE (3, a0)
441 sltu v1,t9,a0
444 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
447 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
452 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*3)
460 sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */
465 PREFETCH_FOR_STORE (4, a0)
466 PREFETCH_FOR_STORE (5, a0)
468 PREFETCH_FOR_STORE (2, a0)
471 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*5)
488 C_ST t0,UNIT(0)(a0)
489 C_ST t1,UNIT(1)(a0)
490 C_ST REG2,UNIT(2)(a0)
491 C_ST REG3,UNIT(3)(a0)
492 C_ST REG4,UNIT(4)(a0)
493 C_ST REG5,UNIT(5)(a0)
494 C_ST REG6,UNIT(6)(a0)
495 C_ST REG7,UNIT(7)(a0)
508 C_ST t0,UNIT(8)(a0)
509 C_ST t1,UNIT(9)(a0)
510 C_ST REG2,UNIT(10)(a0)
511 C_ST REG3,UNIT(11)(a0)
512 C_ST REG4,UNIT(12)(a0)
513 C_ST REG5,UNIT(13)(a0)
514 C_ST REG6,UNIT(14)(a0)
515 C_ST REG7,UNIT(15)(a0)
516 PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
517 bne a0,a3,L(loop16w)
542 C_ST t0,UNIT(0)(a0)
543 C_ST t1,UNIT(1)(a0)
544 C_ST REG2,UNIT(2)(a0)
545 C_ST REG3,UNIT(3)(a0)
546 C_ST REG4,UNIT(4)(a0)
547 C_ST REG5,UNIT(5)(a0)
548 C_ST REG6,UNIT(6)(a0)
549 C_ST REG7,UNIT(7)(a0)
550 PTR_ADDIU a0,a0,UNIT(8)
563 PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
568 PTR_ADDIU a0,a0,UNIT(1)
570 bne a0,a3,L(wordCopy_loop)
571 C_ST REG3,UNIT(-1)(a0)
582 sw REG3,0(a0)
583 PTR_ADDIU a0,a0,4
590 PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
593 PTR_ADDIU a0,a0,1
595 bne a0,a3,L(lastbloop)
596 sb v1,-1(a0)
610 andi t9,a0,3
616 PTR_ADDU a3,a0,a3
620 PTR_ADDIU a0,a0,4
622 bne a0,a3,L(wcopy_loop)
623 sw REG3,-4(a0)
646 C_STHI v1,UNIT(0)(a0)
647 PTR_ADDU a0,a0,a3
661 PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
664 PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
671 PREFETCH_FOR_STORE (1, a0)
672 PREFETCH_FOR_STORE (2, a0)
673 PREFETCH_FOR_STORE (3, a0)
677 sltu v1,t9,a0
680 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
683 PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
692 sltu v1,t9,a0
696 PREFETCH_FOR_STORE (4, a0)
697 PREFETCH_FOR_STORE (5, a0)
712 C_ST t0,UNIT(0)(a0)
713 C_ST t1,UNIT(1)(a0)
714 C_ST REG2,UNIT(2)(a0)
715 C_ST REG3,UNIT(3)(a0)
716 C_ST REG4,UNIT(4)(a0)
717 C_ST REG5,UNIT(5)(a0)
718 C_ST REG6,UNIT(6)(a0)
719 C_ST REG7,UNIT(7)(a0)
737 C_ST t0,UNIT(8)(a0)
738 C_ST t1,UNIT(9)(a0)
739 C_ST REG2,UNIT(10)(a0)
740 C_ST REG3,UNIT(11)(a0)
741 C_ST REG4,UNIT(12)(a0)
742 C_ST REG5,UNIT(13)(a0)
743 C_ST REG6,UNIT(14)(a0)
744 C_ST REG7,UNIT(15)(a0)
745 PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
746 bne a0,a3,L(ua_loop16w)
778 C_ST t0,UNIT(0)(a0)
779 C_ST t1,UNIT(1)(a0)
780 C_ST REG2,UNIT(2)(a0)
781 C_ST REG3,UNIT(3)(a0)
782 C_ST REG4,UNIT(4)(a0)
783 C_ST REG5,UNIT(5)(a0)
784 C_ST REG6,UNIT(6)(a0)
785 C_ST REG7,UNIT(7)(a0)
786 PTR_ADDIU a0,a0,UNIT(8)
795 PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
801 PTR_ADDIU a0,a0,UNIT(1)
803 bne a0,a3,L(ua_wordCopy_loop)
804 C_ST v1,UNIT(-1)(a0)
809 PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
812 PTR_ADDIU a0,a0,1
814 bne a0,a3,L(ua_smallCopy_loop)
815 sb v1,-1(a0)
836 PTR_ADDU REG6, a0, a3; /* REG6 is the dst address after loop. */ \
843 PTR_ADDIU a0, a0, UNIT(1); /* Increment destination pointer. */ \
846 bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \
847 C_ST REG3, UNIT(-1)(a0); \