Lines Matching full:1
24 #define _absb_(src, dest) __asm__("absb %1, %0" : "=r" (dest) : \
26 #define _absw_(src, dest) __asm__("absw %1,%0" : "=r" (dest) : \
28 #define _absd_(src, dest) __asm__("absd %1, %0" : "=r" (dest) : \
32 #define _addb_(src, dest) __asm__("addb %1, %0" : "=r" (dest) : \
34 #define _addub_(src, dest) __asm__("addub %1, %0" : "=r" (dest) : \
36 #define _addw_(src, dest) __asm__("addw %1, %0" : "=r" (dest) : \
38 #define _adduw_(src, dest) __asm__("adduw %1, %0" : "=r" (dest) : \
40 #define _addd_(src, dest) __asm__("addd %1, %0" : "=r" (dest) : \
42 #define _addud_(src, dest) __asm__("addud %1, %0" : "=r" (dest) : \
45 #define _addcb_(src, dest) __asm__("addcb %1, %0" : "=r" (dest) : \
47 #define _addcw_(src, dest) __asm__("addcw %1, %0" : "=r" (dest) : \
49 #define _addcd_(src, dest) __asm__("addcd %1, %0" : "=r" (dest) : \
52 #define _addqb_(src, dest) __asm__("addqb %1, %0" : "=r" (dest) : \
54 #define _addqw_(src, dest) __asm__("addqw %1, %0" : "=r" (dest) : \
56 #define _addqd_(src, dest) __asm__("addqd %1, %0" : "=r" (dest) : \
61 #define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \
63 #define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \
65 #define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \
69 #define _bswap_(src, dest) __asm__("bswap %1,%0" : "=r" (dest) : \
72 #define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \
74 #define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \
76 #define _cbitd_(pos, dest) __asm__("cbitd %1,%0" : "=r" (dest) : \
80 #define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \
82 #define _cmpw_(src1,src2) __asm__("cmpw %0,%1" : /* no output */ \
84 #define _cmpd_(src1,src2) __asm__("cmpd %0,%1" : /* no output */ \
88 #define _cntl1b_(src, dest) __asm__("cntl1b %1,%0" : "=r" (dest) : \
90 #define _cntl1w_(src, dest) __asm__("cntl1w %1,%0" : "=r" (dest) : \
92 #define _cntl1d_(src, dest) __asm__("cntl1d %1,%0" : "=r" (dest) : \
96 #define _cntl0b_(src, dest) __asm__("cntl0b %1,%0" : "=r" (dest) : \
98 #define _cntl0w_(src, dest) __asm__("cntl0w %1,%0" : "=r" (dest) : \
100 #define _cntl0d_(src, dest) __asm__("cntl0d %1,%0" : "=r" (dest) : \
104 #define _cntlsb_(src, dest) __asm__("cntlsb %1,%0" : "=r" (dest) : \
106 #define _cntlsw_(src, dest) __asm__("cntlsw %1,%0" : "=r" (dest) : \
108 #define _cntlsd_(src, dest) __asm__("cntlsd %1,%0" : "=r" (dest) : \
130 #define _loadb_(base,dest) __asm__("loadb %1,%0" : "=r" (dest) : \
132 #define _loadw_(base,dest) __asm__("loadw %1,%0" : "=r" (dest) : \
134 #define _loadd_(base,dest) __asm__("loadd %1,%0" : "=r" (dest) : \
138 #define _loadm_(src, mask) __asm__("loadm %0,%1" : /* No output */ : \
140 #define _loadmp_(src, mask) __asm__("loadmp %0,%1" : /* No output */ : \
144 #define _macsb_(hi, lo, src1, src2) __asm__("macsb %1,%0" \
147 #define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \
150 #define _macsd_(hi, lo, src1, src2) __asm__("macsd %1,%0" \
153 #define _macub_(hi, lo, src1, src2) __asm__("macub %1,%0" \
156 #define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \
159 #define _macud_(hi, lo, src1, src2) __asm__("macud %1,%0" \
164 #define _macqb_(src1, src2) __asm__("macqb %1,%0" \
167 #define _macqw_(src1, src2) __asm__("macqw %1,%0" \
170 #define _macqd_(src1, src2) __asm__("macqd %1,%0" \
175 #define _maxsb_(src, dest) __asm__("maxsb %1,%0" : "=r" (dest) : \
177 #define _maxsw_(src, dest) __asm__("maxsw %1,%0" : "=r" (dest) : \
179 #define _maxsd_(src, dest) __asm__("maxsd %1,%0" : "=r" (dest) : \
181 #define _maxub_(src, dest) __asm__("maxub %1,%0" : "=r" (dest) : \
183 #define _maxuw_(src, dest) __asm__("maxuw %1,%0" : "=r" (dest) : \
185 #define _maxud_(src, dest) __asm__("maxud %1,%0" : "=r" (dest) : \
189 #define _minsb_(src, dest) __asm__("minsb %1,%0" : "=r" (dest) : \
191 #define _minsw_(src, dest) __asm__("minsw %1,%0" : "=r" (dest) : \
193 #define _minsd_(src, dest) __asm__("minsd %1,%0" : "=r" (dest) : \
195 #define _minub_(src, dest) __asm__("minub %1,%0" : "=r" (dest) : \
197 #define _minuw_(src, dest) __asm__("minuw %1,%0" : "=r" (dest) : \
199 #define _minud_(src, dest) __asm__("minud %1,%0" : "=r" (dest) : \
203 #define _movb_(src, dest) __asm__("movb %1,%0" : "=r" (dest) : \
205 #define _movw_(src, dest) __asm__("movw %1,%0" : "=r" (dest) : \
207 #define _movd_(src, dest) __asm__("movd %1,%0" : "=r" (dest) : \
217 #define _mulsbw_(src, dest) __asm__("mulsbw %1,%0" : "=r" (dest) : \
219 #define _mulubw_(src, dest) __asm__("mulubw %1,%0" : "=r" (dest) : \
221 #define _mulswd_(src, dest) __asm__("mulswd %1,%0" : "=r" (dest) : \
223 #define _muluwd_(src, dest) __asm__("muluwd %1,%0" : "=r" (dest) : \
225 #define _mulb_(src, dest) __asm__("mulb %1,%0" : "=r" (dest) : \
227 #define _mulw_(src, dest) __asm__("mulw %1,%0" : "=r" (dest) : \
229 #define _muld_(src, dest) __asm__("muld %1,%0" : "=r" (dest) : \
239 #define _mulqb_(src, dest) __asm__("mulqb %1,%0" : "=r" (dest) : \
241 #define _mulqw_(src, dest) __asm__("mulqw %1,%0" : "=r" (dest) : \
248 #define _negb_(src, dest) __asm__("negb %1,%0" : "=r" (dest) : \
250 #define _negw_(src, dest) __asm__("negw %1,%0" : "=r" (dest) : \
252 #define _negd_(src, dest) __asm__("negd %1,%0" : "=r" (dest) : \
256 #define _orb_(src, dest) __asm__("orb %1,%0" : "=r" (dest) : \
258 #define _orw_(src, dest) __asm__("orw %1,%0" : "=r" (dest) : \
260 #define _ord_(src, dest) __asm__("ord %1,%0" : "=r" (dest) : \
263 /* Pop 1's Count Instructions */
264 #define _popcntb_(src, dest) __asm__("popcntb %1,%0" : "=r" (dest) : \
266 #define _popcntw_(src, dest) __asm__("popcntw %1,%0" : "=r" (dest) : \
268 #define _popcntd_(src, dest) __asm__("popcntd %1,%0" : "=r" (dest) : \
272 #define _ram_(shift, end, begin, dest, src) __asm__("ram %1, %2, %3, %0, %4" : \
277 #define _rim_(shift, end, begin, dest, src) __asm__("rim %1, %2, %3, %0, %4" : \
287 #define _rotb_(shift, dest) __asm__("rotb %1,%0" : "=r" (dest) : \
289 #define _rotw_(shift, dest) __asm__("rotw %1,%0" : "=r" (dest) : \
291 #define _rotd_(shift, dest) __asm__("rotd %1,%0" : "=r" (dest) : \
293 #define _rotlb_(shift, dest) __asm__("rotlb %1,%0" : "=r" (dest) : \
295 #define _rotlw_(shift, dest) __asm__("rotlw %1,%0" : "=r" (dest) : \
297 #define _rotld_(shift, dest) __asm__("rotld %1,%0" : "=r" (dest) : \
299 #define _rotrb_(shift, dest) __asm__("rotrb %1,%0" : "=r" (dest) : \
301 #define _rotrw_(shift, dest) __asm__("rotrw %1,%0" : "=r" (dest) : \
303 #define _rotrd_(shift, dest) __asm__("rotrd %1,%0" : "=r" (dest) : \
307 #define _sbitb_(pos,dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \
309 #define _sbitw_(pos,dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \
311 #define _sbitd_(pos,dest) __asm__("sbitd %1,%0" : "=mr" (dest) : \
319 #define _sextbw_(src, dest) __asm__("sextbw %1,%0" : "=r" (dest) : \
321 #define _sextbd_(src, dest) __asm__("sextbd %1,%0" : "=r" (dest) : \
323 #define _sextwd_(src, dest) __asm__("sextwd %1,%0" : "=r" (dest) : \
327 #define _sllb_(src, dest) __asm__("sllb %1,%0" : "=r" (dest) : \
329 #define _sllw_(src, dest) __asm__("sllw %1,%0" : "=r" (dest) : \
331 #define _slld_(src, dest) __asm__("slld %1,%0" : "=r" (dest) : \
334 #define _srab_(src, dest) __asm__("srab %1,%0" : "=r" (dest) : \
336 #define _sraw_(src, dest) __asm__("sraw %1,%0" : "=r" (dest) : \
338 #define _srad_(src, dest) __asm__("srad %1,%0" : "=r" (dest) : \
342 #define _srlb_(src, dest) __asm__("srlb %1,%0" : "=r" (dest) : \
344 #define _srlw_(src, dest) __asm__("srlw %1,%0" : "=r" (dest) : \
346 #define _srld_(src, dest) __asm__("srld %1,%0" : "=r" (dest) : \
350 #define _storb_(src,address) __asm__("storb %1,%0" : "=m" (address) : \
352 #define _storw_(src,address) __asm__("storw %1,%0" : "=m" (address) : \
354 #define _stord_(src,address) __asm__("stord %1,%0" : "=m" (address) : \
358 #define _storm_(mask, src) __asm__("storm %1,%0" : /* No output here */ : \
360 #define _stormp_(mask, src) __asm__("stormp %1,%0" : /* No output here */ : \
364 #define _subb_(src, dest) __asm__("subb %1, %0" : "=r" (dest) : \
366 #define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \
368 #define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \
372 #define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \
374 #define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \
376 #define _subcd_(src, dest) __asm__("subcd %1, %0" : "=r" (dest) : \
380 #define _subqb_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \
382 #define _subqw_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \
384 #define _subqd_(src, dest) __asm__("subqd %1,%0" : "=r" (dest) : \
388 #define _tbitb_(pos,dest) __asm__("tbitb %0,%1" : /* No output */ : \
390 #define _tbitw_(pos,dest) __asm__("tbitw %0,%1" : /* No output */ : \
392 #define _tbitd_(pos,dest) __asm__("tbitd %0,%1" : /* No output */ : \
399 #define _xorb_(src, dest) __asm__("xorb %1,%0" : "=r" (dest) : \
401 #define _xorw_(src, dest) __asm__("xorw %1,%0" : "=r" (dest) : \
403 #define _xord_(src, dest) __asm__("xord %1,%0" : "=r" (dest) : \
407 #define _zextbw_(src, dest) __asm__("zextbw %1,%0" : "=r" (dest) : \
409 #define _zextbd_(src, dest) __asm__("zextbd %1,%0" : "=r" (dest) : \
411 #define _zextwd_(src, dest) __asm__("zextwd %1,%0" : "=r" (dest) : \