Lines Matching +full:- +full:- +full:set +full:- +full:config
24 gcc -specs=picolibc.specs
30 example uses Picolibc's semihosting support (`--oslib=semihost`) to
33 gcc -specs=picolibc.specs --oslib=semihost
37 For ARM, QEMU emulates a "mps2-an385" board which has a Cortex-M3
40 arm-none-eabi-gcc -specs=picolibc.specs --oslib=semihost -mcpu=cortex-m3
42 64-bit ARM (aarch64) processors are pretty much the same, so the
43 default target code will run fine on a cortex-a57 processor as
46 aarch64-linux-gnu-gcc -specs=picolibc.specs --oslib-semihost
48 For RISC-V, QEMU lets you specify which CPU core you want, so we'll
49 use something that looks like a SiFive E31 chip. That's a 32-bit
51 compressed) and uses the 'ilp32' ABI (32-bit integer, long and
54 riscv64-unknown-elf-gcc -specs=picolibc.specs
55 --oslib-semihost -march=rv32imac -mabi=ilp32
62 will have two kinds of memory, one for code and read-only data and
63 another kind for read-write data. However, the linker script has no
68 The mps2-an385 has at least 16kB of flash starting at 0. Picolibc
70 instruction of _start. The mps2-an385 also has 64kB of RAM starting
92 For the RISC-V 'spike' model, you can have as much memory as you like,
94 application needs to land there. Picolibc on RISC-V puts _start at the
95 first location in read-only memory, so we set things up like this
106 The `-T` flag is used to specify the linker script in the compile
109 arm-none-eabi-gcc -specs=picolibc.specs --oslib=semihost
110 -mcpu=cortex-m3 -Tarm.ld
112 aarch64-linux-gnu-gcc -specs=picolibc.specs --oslib=semihost
113 -Taarch64.ld
119 (hello-world.c) and where to put the output (hello-world-riscv.elf and
120 hello-world-arm.elf):
122 riscv64-unknown-elf-gcc --specs=picolibc.specs --oslib=semihost
123 -march=rv32imac -mabi=ilp32 -Thello-world-riscv.ld -o
124 hello-world-riscv.elf hello-world.c
126 arm-none-eabi-gcc --specs=picolibc.specs --oslib=semihost
127 -mcpu=cortex-m3 -Thello-world-arm.ld -o hello-world-arm.elf
128 hello-world.c
132 To run the hello-world example under qemu, we need to construct a
134 (`-semihosting-config enable=on`), disabling the monitor interface
135 (-monitor none), the emulated UART (-serial none) and the graphical
136 interface (`-nographic).
138 For arm, we're using the mps2-an385
140 qemu-system-arm -semihosting-config enable=on -monitor none
141 -serial none -nographic
142 -machine mps2-an385,accel=tcg
143 -kernel hello-world-arm.elf
146 processor we want. In this case, we'll use the cortex-a57:
148 qemu-system-aarch64 -semihosting-config enable=on -monitor none
149 -serial none -nographic
150 -machine virt -cpu cortex-a57
151 -kernel hello-world-aarch64.elf
153 Risc-V is similar to aarch64 in providing a virtual host into which
156 qemu-system-riscv32 -semihosting-config enable=on -monitor none
157 -serial none -nographic
158 -machine virt,accel=tcg -cpu rv32 -bios none
159 -kernel hello-world-riscv.elf