Lines Matching refs:in
21 We are not interested in modeling the particularities of the HW when
34 could, anyhow, not be better than what is described in those.<br>
48 realize, will be modeled as being instantaneous in simulation time.
54 Such processes will be modeled in a bit more complex way:
57 * When needed these timers will be set at a point in the future where some
59 * Whenever that time is reached, the HW scheduler will call a function in that
63 in compile time.
69 Whenever a HW model updates its event timer, it will call a function in the HW scheduler.
75 Note that several HW submodules may be scheduled to run in the same microsecond.
76 In this case, they will be handled in different "delta cycles" in that same microsecond.
78 in the same order relative to other HW events which may be schedule in the
80 Note also, that any HW submodule may schedule a new event to be called in the
81 same microsecond in which it is running. This can be done for any purpose,
84 When they do so, their "event|task runner" will be called right after in the
91 This structure will be allocated somewhere in the process memory, but certainly
92 not in the same address as in the real HW.
93 Therefore any access to the real registers must be, in some way, corrected
96 nRF HAL MDK macros which, in real HW point to the peripherals base addresses, which points
99 Writing to this structure in itself will only cause that memory location to be
101 that happens in the real HW (a register is changed, which later may be
104 side-effect, that is, something else to happen in the HW.
105 For example, in real HW, writing a `1` to
111 In Zephyr's nrf*bsim case, this is done in the replacement nRFx HAL function.
128 The actual HW models of the SOC peripherals are normally split in one file per peripheral.
164 specified in the linked documentation.
166 ## Integrating these models in another system
174 They rely on an overall scheduler triggering (calling) them in
184 they are run in the same order consistently.
186 The events timers represent, in microseconds, when the models need to perform
221 (this second case is how it is done in Zephyr's nrf*bsim targets)