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41 #define cpuss_0_dap_0_ENABLED 1U
42 #define srss_0_clock_0_ENABLED 1U
43 #define srss_0_clock_0_altsystickclk_0_ENABLED 1U
44 #define srss_0_clock_0_bakclk_0_ENABLED 1U
45 #define srss_0_clock_0_fastclk_0_ENABLED 1U
46 #define srss_0_clock_0_fll_0_ENABLED 1U
47 #define srss_0_clock_0_hfclk_0_ENABLED 1U
49 #define srss_0_clock_0_hfclk_2_ENABLED 1U
51 #define srss_0_clock_0_hfclk_3_ENABLED 1U
53 #define srss_0_clock_0_hfclk_4_ENABLED 1U
55 #define srss_0_clock_0_ilo_0_ENABLED 1U
56 #define srss_0_clock_0_imo_0_ENABLED 1U
57 #define srss_0_clock_0_lfclk_0_ENABLED 1U
59 #define srss_0_clock_0_pathmux_0_ENABLED 1U
60 #define srss_0_clock_0_pathmux_1_ENABLED 1U
61 #define srss_0_clock_0_pathmux_2_ENABLED 1U
62 #define srss_0_clock_0_periclk_0_ENABLED 1U
63 #define srss_0_clock_0_pll_0_ENABLED 1U
64 #define srss_0_clock_0_pll_1_ENABLED 1U
65 #define srss_0_clock_0_slowclk_0_ENABLED 1U
66 #define srss_0_clock_0_timerclk_0_ENABLED 1U
67 #define srss_0_clock_0_wco_0_ENABLED 1U