Lines Matching refs:__IO
144 …__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Addre…
145 …__IO uint32_t IER; /*!< ADC Interrupt Enable register, Addre…
146 …__IO uint32_t CR; /*!< ADC Control register, Addre…
147 …__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Addre…
148 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre…
149 …__IO uint32_t SMPR; /*!< ADC Sampling time register, Addre…
152 …__IO uint32_t TR; /*!< ADC watchdog threshold register, Addre…
154 …__IO uint32_t CHSELR; /*!< ADC channel selection register, Addre…
156 …__IO uint32_t DR; /*!< ADC data register, Addre…
158 …__IO uint32_t CALFACT; /*!< ADC data register, Addre…
163 __IO uint32_t CCR;
172 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
173 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
174 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
175 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
176 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
177 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
178 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
179 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
180 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
181 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
182 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
183 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
192 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
197 …__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several …
207 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x0…
208 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x0…
211 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x0…
213 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x1…
214 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x1…
223 …__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00…
224 …__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04…
225 …__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08…
226 …__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C…
235 __IO uint32_t CCR; /*!< DMA channel x configuration register */
236 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
237 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
238 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
243 …__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00…
244 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04…
249 …__IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8…
258 …__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00…
259 …__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04…
260 …__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08…
261 …__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C…
262 …__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10…
263 …__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14…
271 …__IO uint32_t ACR; /*!< Access control register, Address offset: 0x0…
272 …__IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x0…
273 …__IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x0…
274 …__IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0…
275 …__IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x1…
276 …__IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x1…
277 …__IO uint32_t SR; /*!< Status register, Address offset: 0x1…
278 …__IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1…
279 …__IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x2…
280 …__IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x2…
281 …__IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x8…
290 …__IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00…
291 …__IO uint32_t USER; /*!< user register, Address offset: 0x04…
292 …__IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08…
293 …__IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C…
294 …__IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10…
304 …__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00…
305 …__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04…
306 …__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08…
307 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C…
308 …__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10…
309 …__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14…
310 …__IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18…
311 …__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C…
312 …__IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20…
313 …__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28…
321 …__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00…
322 …__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04…
323 …__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08…
324 …__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C…
325 …__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10…
326 …__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14…
327 …__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18…
328 …__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C…
337 …__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offs…
338 …__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offs…
339 …__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offs…
341 …__IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offs…
352 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
353 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
354 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
355 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
356 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
357 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
358 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
359 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
360 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
361 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
362 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
371 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
372 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
373 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
374 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
375 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
383 …__IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x…
384 …__IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x…
385 …__IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x…
386 …__IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x…
387 …__IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x…
388 …__IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x…
389 …__IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x…
390 …__IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x…
391 …__IO uint32_t CR ; /*!< Configuration register, Address offset: 0x…
400 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
401 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
409 …__IO uint32_t CR; /*!< RCC clock control register, Ad…
410 …__IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Ad…
411 …__IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Ad…
412 …__IO uint32_t CFGR; /*!< RCC Clock configuration register, Ad…
413 …__IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Ad…
414 …__IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Ad…
415 …__IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Ad…
416 …__IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Ad…
417 …__IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Ad…
418 …__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Ad…
419 …__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Ad…
420 …__IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Ad…
421 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad…
422 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Ad…
423 …__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Ad…
424 …__IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Ad…
425 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad…
426 …__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Ad…
427 …__IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Ad…
428 …__IO uint32_t CCIPR; /*!< RCC clock configuration register, Ad…
429 …__IO uint32_t CSR; /*!< RCC Control/status register, Ad…
437 …__IO uint32_t TR; /*!< RTC time register, Address …
438 …__IO uint32_t DR; /*!< RTC date register, Address …
439 …__IO uint32_t CR; /*!< RTC control register, Address …
440 …__IO uint32_t ISR; /*!< RTC initialization and status register, Address …
441 …__IO uint32_t PRER; /*!< RTC prescaler register, Address …
442 …__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address …
444 …__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address …
445 …__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address …
446 …__IO uint32_t WPR; /*!< RTC write protection register, Address …
447 …__IO uint32_t SSR; /*!< RTC sub second register, Address …
448 …__IO uint32_t SHIFTR; /*!< RTC shift control register, Address …
449 …__IO uint32_t TSTR; /*!< RTC time stamp time register, Address …
450 …__IO uint32_t TSDR; /*!< RTC time stamp date register, Address …
451 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
452 …__IO uint32_t CALR; /*!< RTC calibration register, Address …
453 …__IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address …
454 …__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address …
455 …__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address …
456 …__IO uint32_t OR; /*!< RTC option register, Address …
457 …__IO uint32_t BKP0R; /*!< RTC backup register 0, Address …
458 …__IO uint32_t BKP1R; /*!< RTC backup register 1, Address …
459 …__IO uint32_t BKP2R; /*!< RTC backup register 2, Address …
460 …__IO uint32_t BKP3R; /*!< RTC backup register 3, Address …
461 …__IO uint32_t BKP4R; /*!< RTC backup register 4, Address …
470 …__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: …
471 …__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: …
472 …__IO uint32_t SR; /*!< SPI Status register, Address offset: …
473 …__IO uint32_t DR; /*!< SPI data register, Address offset: …
474 …__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: …
475 …__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: …
476 …__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: …
477 …__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: …
478 …__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: …
486 …__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
487 …__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
488 …__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
489 …__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
490 …__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
491 …__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
492 …__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
493 …__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
494 …__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
495 …__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
496 …__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
497 …__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
499 …__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
500 …__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
501 …__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
502 …__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
504 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
505 …__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
506 …__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
514 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
515 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
516 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
517 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
518 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
519 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
520 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
521 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
522 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
523 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
524 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
532 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
533 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
534 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */