Lines Matching refs:__IO
146 …__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Addre…
147 …__IO uint32_t IER; /*!< ADC Interrupt Enable register, Addre…
148 …__IO uint32_t CR; /*!< ADC Control register, Addre…
149 …__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Addre…
150 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre…
151 …__IO uint32_t SMPR; /*!< ADC Sampling time register, Addre…
154 …__IO uint32_t TR; /*!< ADC watchdog threshold register, Addre…
156 …__IO uint32_t CHSELR; /*!< ADC channel selection register, Addre…
158 …__IO uint32_t DR; /*!< ADC data register, Addre…
160 …__IO uint32_t CALFACT; /*!< ADC data register, Addre…
165 __IO uint32_t CCR;
175 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
180 …__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several …
190 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x0…
191 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x0…
194 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x0…
196 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x1…
197 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x1…
206 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
207 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
208 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
209 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
218 …__IO uint32_t CR; /*!< DAC control register, Address…
219 …__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address…
220 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address…
221 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address…
222 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address…
223 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address…
224 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address…
225 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address…
226 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address…
227 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address…
228 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address…
229 …__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address…
230 …__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address…
231 …__IO uint32_t SR; /*!< DAC status register, Address…
240 …__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00…
241 …__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04…
242 …__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08…
243 …__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C…
252 __IO uint32_t CCR; /*!< DMA channel x configuration register */
253 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
254 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
255 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
260 …__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00…
261 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04…
266 …__IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8…
275 …__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00…
276 …__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04…
277 …__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08…
278 …__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C…
279 …__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10…
280 …__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14…
288 …__IO uint32_t ACR; /*!< Access control register, Address offset: 0x0…
289 …__IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x0…
290 …__IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x0…
291 …__IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0…
292 …__IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x1…
293 …__IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x1…
294 …__IO uint32_t SR; /*!< Status register, Address offset: 0x1…
295 …__IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1…
296 …__IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x2…
297 …__IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x2…
298 …__IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x8…
307 …__IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00…
308 …__IO uint32_t USER; /*!< user register, Address offset: 0x04…
309 …__IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08…
310 …__IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C…
311 …__IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10…
321 …__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00…
322 …__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04…
323 …__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08…
324 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C…
325 …__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10…
326 …__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14…
327 …__IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18…
328 …__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C…
329 …__IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20…
330 …__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28…
338 …__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00…
339 …__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04…
340 …__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08…
341 …__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C…
342 …__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10…
343 …__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14…
344 …__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18…
345 …__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C…
354 …__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offs…
355 …__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offs…
356 …__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offs…
358 …__IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offs…
369 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
370 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
371 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
372 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
373 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
374 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
375 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
376 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
377 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
378 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
379 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
388 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
389 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
390 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
391 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
392 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
400 …__IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x…
401 …__IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x…
402 …__IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x…
403 …__IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x…
404 …__IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x…
405 …__IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x…
406 …__IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x…
407 …__IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x…
408 …__IO uint32_t CR ; /*!< Configuration register, Address offset: 0x…
417 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
418 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
426 …__IO uint32_t CR; /*!< RCC clock control register, Ad…
427 …__IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Ad…
428 …__IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Ad…
429 …__IO uint32_t CFGR; /*!< RCC Clock configuration register, Ad…
430 …__IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Ad…
431 …__IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Ad…
432 …__IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Ad…
433 …__IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Ad…
434 …__IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Ad…
435 …__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Ad…
436 …__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Ad…
437 …__IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Ad…
438 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad…
439 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Ad…
440 …__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Ad…
441 …__IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Ad…
442 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad…
443 …__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Ad…
444 …__IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Ad…
445 …__IO uint32_t CCIPR; /*!< RCC clock configuration register, Ad…
446 …__IO uint32_t CSR; /*!< RCC Control/status register, Ad…
454 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
455 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
456 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
464 …__IO uint32_t TR; /*!< RTC time register, Address …
465 …__IO uint32_t DR; /*!< RTC date register, Address …
466 …__IO uint32_t CR; /*!< RTC control register, Address …
467 …__IO uint32_t ISR; /*!< RTC initialization and status register, Address …
468 …__IO uint32_t PRER; /*!< RTC prescaler register, Address …
469 …__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address …
471 …__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address …
472 …__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address …
473 …__IO uint32_t WPR; /*!< RTC write protection register, Address …
474 …__IO uint32_t SSR; /*!< RTC sub second register, Address …
475 …__IO uint32_t SHIFTR; /*!< RTC shift control register, Address …
476 …__IO uint32_t TSTR; /*!< RTC time stamp time register, Address …
477 …__IO uint32_t TSDR; /*!< RTC time stamp date register, Address …
478 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
479 …__IO uint32_t CALR; /*!< RTC calibration register, Address …
480 …__IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address …
481 …__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address …
482 …__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address …
483 …__IO uint32_t OR; /*!< RTC option register, Address …
484 …__IO uint32_t BKP0R; /*!< RTC backup register 0, Address …
485 …__IO uint32_t BKP1R; /*!< RTC backup register 1, Address …
486 …__IO uint32_t BKP2R; /*!< RTC backup register 2, Address …
487 …__IO uint32_t BKP3R; /*!< RTC backup register 3, Address …
488 …__IO uint32_t BKP4R; /*!< RTC backup register 4, Address …
497 …__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: …
498 …__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: …
499 …__IO uint32_t SR; /*!< SPI Status register, Address offset: …
500 …__IO uint32_t DR; /*!< SPI data register, Address offset: …
501 …__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: …
502 …__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: …
503 …__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: …
504 …__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: …
505 …__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: …
513 …__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
514 …__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
515 …__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
516 …__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
517 …__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
518 …__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
519 …__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
520 …__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
521 …__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
522 …__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
523 …__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
524 …__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
526 …__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
527 …__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
528 …__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
529 …__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
531 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
532 …__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
533 …__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
541 …__IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
542 …__IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
543 …__IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
544 …__IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
545 …__IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
547 …__IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
549 …__IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
551 …__IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
553 …__IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
554 …__IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-5…
562 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
563 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
564 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
565 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
566 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
567 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
568 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
569 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
570 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
571 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
572 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
580 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
581 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
582 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
590 …__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 *…
591 __IO uint16_t RESERVED0; /*!< Reserved */
592 …__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
593 __IO uint16_t RESERVED1; /*!< Reserved */
594 …__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
595 __IO uint16_t RESERVED2; /*!< Reserved */
596 …__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C *…
597 __IO uint16_t RESERVED3; /*!< Reserved */
598 …__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
599 __IO uint16_t RESERVED4; /*!< Reserved */
600 …__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
601 __IO uint16_t RESERVED5; /*!< Reserved */
602 …__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
603 __IO uint16_t RESERVED6; /*!< Reserved */
604 …__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
605 __IO uint16_t RESERVED7[17]; /*!< Reserved */
606 …__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
607 __IO uint16_t RESERVED8; /*!< Reserved */
608 …__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
609 __IO uint16_t RESERVED9; /*!< Reserved */
610 …__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
611 __IO uint16_t RESERVEDA; /*!< Reserved */
612 …__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
613 __IO uint16_t RESERVEDB; /*!< Reserved */
614 …__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
615 __IO uint16_t RESERVEDC; /*!< Reserved */
616 …__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
617 __IO uint16_t RESERVEDD; /*!< Reserved */
618 …__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
619 __IO uint16_t RESERVEDE; /*!< Reserved */