Lines Matching refs:APB1PERIPH_BASE
655 #define APB1PERIPH_BASE PERIPH_BASE macro
660 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
661 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
662 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
663 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
664 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
665 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
666 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400U)
667 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
668 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
669 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
670 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
671 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
672 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
673 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
674 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
675 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
678 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base…
679 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base a…
682 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
683 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
684 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U)
685 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U)
686 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU)