233             MAP_I2SIntDisable(I2S_BASE, 0xFFFFFFFF);  in I2S_open()
255     MAP_I2SIntDisable(I2S_BASE, 0xFFFFFFFF);  in I2S_close()
323     MAP_I2SIntEnable(I2S_BASE,   I2S_INT_RSYNCERR | I2S_INT_XSYNCERR);  in I2S_startClocks()
330     MAP_I2SEnable(I2S_BASE, (unsigned long)mode);  in I2S_startClocks()
343     MAP_I2SIntDisable(I2S_BASE,    I2S_INT_RSYNCERR | I2S_INT_XSYNCERR);  in I2S_stopClocks()
350     MAP_I2SDisable(I2S_BASE);  in I2S_stopClocks()
373             HWREG(I2S_BASE + MCASP_O_EVTCTLR) |= (((I2S_INT_RDATA | I2S_INT_ROVRN) >> 16) & 0xFF);  in I2S_startRead()
382             MAP_I2SRxFIFOEnable(I2S_BASE, object->udmaArbLength, object->noOfInputs);  in I2S_startRead()
387 …HWREG(I2S_BASE + MCASP_O_EVTCTLR) |= (((I2S_INT_RDMA | I2S_INT_ROVRN | I2S_INT_RLAST) >> 16) & 0xF…  in I2S_startRead()
393             MAP_I2SSerializerConfig(I2S_BASE, SD0->dataLine, I2S_SER_MODE_RX, I2S_INACT_LOW_LEVEL);  in I2S_startRead()
396             MAP_I2SSerializerConfig(I2S_BASE, SD1->dataLine, I2S_SER_MODE_RX, I2S_INACT_LOW_LEVEL);  in I2S_startRead()
420             HWREG(I2S_BASE + MCASP_O_EVTCTLX) |= ((I2S_INT_XDATA | I2S_INT_XUNDRN) & 0xFF);  in I2S_startWrite()
429             MAP_I2STxFIFOEnable(I2S_BASE, object->udmaArbLength, object->noOfOutputs);  in I2S_startWrite()
434 …     HWREG(I2S_BASE + MCASP_O_EVTCTLX) |= ((I2S_INT_XDMA | I2S_INT_XLAST | I2S_INT_XUNDRN) & 0xFF);  in I2S_startWrite()
440             MAP_I2SSerializerConfig(I2S_BASE, SD0->dataLine, I2S_SER_MODE_TX, I2S_INACT_LOW_LEVEL);  in I2S_startWrite()
443             MAP_I2SSerializerConfig(I2S_BASE, SD1->dataLine, I2S_SER_MODE_TX, I2S_INACT_LOW_LEVEL);  in I2S_startWrite()
469             MAP_I2SIntDisable(I2S_BASE, I2S_INT_RDMA | I2S_INT_ROVRN );  in I2S_stopRead()
477 …       MAP_I2SSerializerConfig(I2S_BASE, SD0->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in I2S_stopRead()
480 …       MAP_I2SSerializerConfig(I2S_BASE, SD1->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in I2S_stopRead()
507             MAP_I2SIntDisable(I2S_BASE, I2S_INT_XDMA | I2S_INT_XUNDRN);  in I2S_stopWrite()
515 …       MAP_I2SSerializerConfig(I2S_BASE, SD0->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in I2S_stopWrite()
518 …       MAP_I2SSerializerConfig(I2S_BASE, SD1->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in I2S_stopWrite()
555     uint32_t rawInterruptStatus = (uint32_t)MAP_I2SIntStatus(I2S_BASE);  in I2S_hwiIntFxn()
557         MAP_I2SIntClear(I2S_BASE,  rawInterruptStatus & ~I2S_STS_RDATA & ~I2S_STS_XDATA);  in I2S_hwiIntFxn()
560         MAP_I2SIntClear(I2S_BASE, rawInterruptStatus);  in I2S_hwiIntFxn()
659             MAP_I2SIntDisable(I2S_BASE, I2S_INT_RLAST | I2S_INT_RDMA | I2S_INT_ROVRN);  in updateDataReadDMA()
662             MAP_I2SRxFIFODisable(I2S_BASE);  in updateDataReadDMA()
665 …       MAP_I2SSerializerConfig(I2S_BASE, SD0->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in updateDataReadDMA()
668 …       MAP_I2SSerializerConfig(I2S_BASE, SD1->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in updateDataReadDMA()
719             MAP_I2SIntDisable(I2S_BASE, I2S_INT_XDMA | I2S_INT_XUNDRN | I2S_INT_XLAST);  in updateDataWriteDMA()
722             MAP_I2STxFIFODisable(I2S_BASE);  in updateDataWriteDMA()
725 …       MAP_I2SSerializerConfig(I2S_BASE, SD0->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in updateDataWriteDMA()
728 …       MAP_I2SSerializerConfig(I2S_BASE, SD1->dataLine, I2S_SER_MODE_DISABLE, I2S_INACT_LOW_LEVEL);  in updateDataWriteDMA()
811 …            dataKO |= MAP_I2SDataGetNonBlocking(I2S_BASE, SD0->dataLine, (unsigned long*)ptrValue);  in updateDataReadCPU()
825 …            dataKO |= MAP_I2SDataGetNonBlocking(I2S_BASE, SD1->dataLine, (unsigned long*)ptrValue);  in updateDataReadCPU()
840     MAP_I2SIntClear(I2S_BASE,I2S_STS_RDATA);  in updateDataReadCPU()
869                 dataKO |= MAP_I2SDataPutNonBlocking(I2S_BASE, SD0->dataLine, Value);  in updateDataWriteCPU()
884                 dataKO |= MAP_I2SDataPutNonBlocking(I2S_BASE, SD1->dataLine, Value);  in updateDataWriteCPU()
900     MAP_I2SIntClear(I2S_BASE,I2S_STS_XDATA);  in updateDataWriteCPU()
1239     HWREG(I2S_BASE + MCASP_O_AHCLKXCTL) = (MCASP_AHCLKXCTL_HCLKXM_DEFAULT|ulHClkDiv);  in configSCK()
1242 …    HWREG(I2S_BASE + MCASP_O_ACLKXCTL)  = (((object->samplingEdge << 7)   & MCASP_ACLKXCTL_CLKXP) |  in configSCK()
1247     HWREG(I2S_BASE + MCASP_O_AHCLKRCTL) = (MCASP_AHCLKRCTL_HCLKRM_DEFAULT|ulHClkDiv);  in configSCK()
1250 …    HWREG(I2S_BASE + MCASP_O_ACLKRCTL)  = (((object->samplingEdge << 7)   & MCASP_ACLKRCTL_CLKRP) |  in configSCK()
1268         HWREG(I2S_BASE + MCASP_O_RXFMCTL) =  (  MCASP_RXFMCTL_RMOD_DEFAULT                       |  in configWS()
1275     HWREG(I2S_BASE + MCASP_O_TXFMCTL) =  (  MCASP_TXFMCTL_XMOD_DEFAULT                       |  in configWS()
1315 …HWREG(I2S_BASE + MCASP_O_RXFMT) = (((object->dataShift        << MCASP_RXFMT_RDATDLY_S) & MCASP_RX…  in configSerialFormat()
1320         HWREG(I2S_BASE + MCASP_O_RXMASK) = object->sampleMask;  in configSerialFormat()
1321         HWREG(I2S_BASE + MCASP_O_RXTDM) = channelsToActivate;  in configSerialFormat()
1327 …HWREG(I2S_BASE + MCASP_O_TXFMT) = (((object->dataShift        << MCASP_TXFMT_XDATDLY_S) & MCASP_TX…  in configSerialFormat()
1332     HWREG(I2S_BASE + MCASP_O_TXMASK) = object->sampleMask;  in configSerialFormat()
1333     HWREG(I2S_BASE + MCASP_O_TXTDM) = channelsToActivate;  in configSerialFormat()