69     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in UART_initModule()
72     EUSCI_A_CMSIS(moduleInstance)->CTLW0 =  in UART_initModule()
73             (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)  in UART_initModule()
78         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;  in UART_initModule()
80         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;  in UART_initModule()
84         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;  in UART_initModule()
86         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;  in UART_initModule()
92         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;  in UART_initModule()
95         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;  in UART_initModule()
96         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;  in UART_initModule()
99         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;  in UART_initModule()
100         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;  in UART_initModule()
110     EUSCI_A_CMSIS(moduleInstance)->CTLW0 =  in UART_initModule()
111             (EUSCI_A_CMSIS(moduleInstance)->CTLW0  in UART_initModule()
141     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;  in UART_enableModule()
147     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in UART_disableModule()
167     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;  in UART_setDormant()
172     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;  in UART_resetDormant()
178     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;  in UART_transmitAddress()
187     BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;  in UART_transmitBreak()
191             == (EUSCI_A_CMSIS(moduleInstance)->CTLW0  in UART_transmitBreak()
251     EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;  in UART_enableInterrupt()
276     EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;  in UART_disableInterrupt()
307     intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;  in UART_getEnabledInterruptStatus()