85         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in SPI_initMaster()
94         EUSCI_A_CMSIS(moduleInstance)->CTLW0 =  in SPI_initMaster()
95                 (EUSCI_A_CMSIS(moduleInstance)->CTLW0  in SPI_initMaster()
141         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in SPI_initMaster()
150         EUSCI_B_CMSIS(moduleInstance)->CTLW0 =  in SPI_initMaster()
151                 (EUSCI_B_CMSIS(moduleInstance)->CTLW0  in SPI_initMaster()
225         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in SPI_initSlave()
228         EUSCI_A_CMSIS(moduleInstance)->CTLW0 =  in SPI_initSlave()
229                 (EUSCI_A_CMSIS(moduleInstance)->CTLW0  in SPI_initSlave()
261         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in SPI_initSlave()
264         EUSCI_B_CMSIS(moduleInstance)->CTLW0 =  in SPI_initSlave()
265                 (EUSCI_B_CMSIS(moduleInstance)->CTLW0  in SPI_initSlave()
567     EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0  in EUSCI_B_SPI_select4PinFunctionality()
589     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_B_SPI_masterChangeClock()
595     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;  in EUSCI_B_SPI_masterChangeClock()
657     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_B_SPI_slaveInit()
660     EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0  in EUSCI_B_SPI_slaveInit()
705     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_B_SPI_changeClockPhasePolarity()
707     EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0  in EUSCI_B_SPI_changeClockPhasePolarity()
711     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;  in EUSCI_B_SPI_changeClockPhasePolarity()
877     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;  in EUSCI_B_SPI_enable()
896     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_B_SPI_disable()
978     EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0  in EUSCI_A_SPI_select4PinFunctionality()
1000     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_A_SPI_masterChangeClock()
1006     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;  in EUSCI_A_SPI_masterChangeClock()
1068     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_A_SPI_slaveInit()
1071     EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0  in EUSCI_A_SPI_slaveInit()
1116     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_A_SPI_changeClockPhasePolarity()
1118     EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0  in EUSCI_A_SPI_changeClockPhasePolarity()
1122     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;  in EUSCI_A_SPI_changeClockPhasePolarity()
1288     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;  in EUSCI_A_SPI_enable()
1307     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;  in EUSCI_A_SPI_disable()