183     if (SCB->VTOR != (uint32_t) g_pfnRAMVectors)  in Interrupt_registerInterrupt()
189         ulValue = SCB->VTOR;  in Interrupt_registerInterrupt()
199         SCB->VTOR = (uint32_t) g_pfnRAMVectors;  in Interrupt_registerInterrupt()
231     SCB->AIRCR = SCB_AIRCR_VECTKEY_Msk | g_pulPriority[bits];  in Interrupt_setPriorityGrouping()
241     ulValue = SCB->AIRCR & NVIC_APINT_PRIGROUP_M;  in Interrupt_getPriorityGrouping()
310         SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;  in Interrupt_enableInterrupt()
316         SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;  in Interrupt_enableInterrupt()
322         SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;  in Interrupt_enableInterrupt()
354         SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA_Msk);  in Interrupt_disableInterrupt()
360         SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA_Msk);  in Interrupt_disableInterrupt()
366         SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA_Msk);  in Interrupt_disableInterrupt()
405         ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA_Msk;  in Interrupt_isEnabled()
411         ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA_Msk;  in Interrupt_isEnabled()
417         ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA_Msk;  in Interrupt_isEnabled()
450         SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk;  in Interrupt_pendInterrupt()
456         SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;  in Interrupt_pendInterrupt()
462         SCB->ICSR |= SCB_ICSR_PENDSTSET_Msk;  in Interrupt_pendInterrupt()
488         SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk;  in Interrupt_unpendInterrupt()
494         SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;  in Interrupt_unpendInterrupt()
517     SCB->VTOR = addr;  in Interrupt_setVectorTableAddress()
522     return SCB->VTOR;  in Interrupt_getVectorTableAddress()
527     SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;  in Interrupt_enableSleepOnIsrExit()
532     SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;  in Interrupt_disableSleepOnIsrExit()