Lines Matching refs:ui32Base
86 _I2CBaseValid(uint32_t ui32Base) in _I2CBaseValid() argument
88 return((ui32Base == I2CA0_BASE)); in _I2CBaseValid()
106 _I2CIntNumberGet(uint32_t ui32Base) in _I2CIntNumberGet() argument
114 ASSERT(_I2CBaseValid(ui32Base)); in _I2CIntNumberGet()
128 if(ppui32I2CIntMap[i8Idx][0] == ui32Base) in _I2CIntNumberGet()
168 I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, in I2CMasterInitExpClk() argument
177 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterInitExpClk()
182 I2CMasterEnable(ui32Base); in I2CMasterInitExpClk()
204 HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; in I2CMasterInitExpClk()
210 if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) in I2CMasterInitExpClk()
214 HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; in I2CMasterInitExpClk()
235 I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) in I2CSlaveInit() argument
240 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveInit()
246 I2CSlaveEnable(ui32Base); in I2CSlaveInit()
251 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; in I2CSlaveInit()
271 I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) in I2CSlaveAddressSet() argument
276 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveAddressSet()
290 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; in I2CSlaveAddressSet()
299 HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; in I2CSlaveAddressSet()
317 I2CMasterEnable(uint32_t ui32Base) in I2CMasterEnable() argument
322 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterEnable()
327 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; in I2CMasterEnable()
342 I2CSlaveEnable(uint32_t ui32Base) in I2CSlaveEnable() argument
347 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveEnable()
352 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; in I2CSlaveEnable()
357 HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; in I2CSlaveEnable()
372 I2CMasterDisable(uint32_t ui32Base) in I2CMasterDisable() argument
377 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterDisable()
382 HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); in I2CMasterDisable()
397 I2CSlaveDisable(uint32_t ui32Base) in I2CSlaveDisable() argument
402 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveDisable()
407 HWREG(ui32Base + I2C_O_SCSR) = 0; in I2CSlaveDisable()
412 HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); in I2CSlaveDisable()
437 I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) in I2CIntRegister() argument
444 ASSERT(_I2CBaseValid(ui32Base)); in I2CIntRegister()
449 ui32Int = _I2CIntNumberGet(ui32Base); in I2CIntRegister()
481 I2CIntUnregister(uint32_t ui32Base) in I2CIntUnregister() argument
488 ASSERT(_I2CBaseValid(ui32Base)); in I2CIntUnregister()
493 ui32Int = _I2CIntNumberGet(ui32Base); in I2CIntUnregister()
520 I2CMasterIntEnable(uint32_t ui32Base) in I2CMasterIntEnable() argument
525 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntEnable()
530 HWREG(ui32Base + I2C_O_MIMR) = 1; in I2CMasterIntEnable()
564 I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CMasterIntEnableEx() argument
569 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntEnableEx()
574 HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; in I2CMasterIntEnableEx()
589 I2CSlaveIntEnable(uint32_t ui32Base) in I2CSlaveIntEnable() argument
594 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntEnable()
599 HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; in I2CSlaveIntEnable()
630 I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CSlaveIntEnableEx() argument
635 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntEnableEx()
640 HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; in I2CSlaveIntEnableEx()
655 I2CMasterIntDisable(uint32_t ui32Base) in I2CMasterIntDisable() argument
660 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntDisable()
665 HWREG(ui32Base + I2C_O_MIMR) = 0; in I2CMasterIntDisable()
687 I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CMasterIntDisableEx() argument
692 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntDisableEx()
697 HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; in I2CMasterIntDisableEx()
712 I2CSlaveIntDisable(uint32_t ui32Base) in I2CSlaveIntDisable() argument
717 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntDisable()
722 HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; in I2CSlaveIntDisable()
744 I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CSlaveIntDisableEx() argument
749 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntDisableEx()
754 HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; in I2CSlaveIntDisableEx()
774 I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) in I2CMasterIntStatus() argument
779 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntStatus()
787 return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); in I2CMasterIntStatus()
791 return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); in I2CMasterIntStatus()
812 I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) in I2CMasterIntStatusEx() argument
817 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntStatusEx()
825 return(HWREG(ui32Base + I2C_O_MMIS)); in I2CMasterIntStatusEx()
829 return(HWREG(ui32Base + I2C_O_MRIS)); in I2CMasterIntStatusEx()
850 I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) in I2CSlaveIntStatus() argument
855 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntStatus()
863 return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); in I2CSlaveIntStatus()
867 return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); in I2CSlaveIntStatus()
888 I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) in I2CSlaveIntStatusEx() argument
893 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntStatusEx()
901 return(HWREG(ui32Base + I2C_O_SMIS)); in I2CSlaveIntStatusEx()
905 return(HWREG(ui32Base + I2C_O_SRIS)); in I2CSlaveIntStatusEx()
932 I2CMasterIntClear(uint32_t ui32Base) in I2CMasterIntClear() argument
937 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntClear()
942 HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; in I2CMasterIntClear()
949 HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; in I2CMasterIntClear()
979 I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CMasterIntClearEx() argument
984 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterIntClearEx()
989 HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; in I2CMasterIntClearEx()
1015 I2CSlaveIntClear(uint32_t ui32Base) in I2CSlaveIntClear() argument
1020 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntClear()
1025 HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; in I2CSlaveIntClear()
1055 I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) in I2CSlaveIntClearEx() argument
1060 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveIntClearEx()
1065 HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; in I2CSlaveIntClearEx()
1086 I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, in I2CMasterSlaveAddrSet() argument
1092 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterSlaveAddrSet()
1098 HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; in I2CMasterSlaveAddrSet()
1116 I2CMasterLineStateGet(uint32_t ui32Base) in I2CMasterLineStateGet() argument
1121 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterLineStateGet()
1126 return(HWREG(ui32Base + I2C_O_MBMON)); in I2CMasterLineStateGet()
1143 I2CMasterBusy(uint32_t ui32Base) in I2CMasterBusy() argument
1148 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterBusy()
1153 if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) in I2CMasterBusy()
1178 I2CMasterBusBusy(uint32_t ui32Base) in I2CMasterBusBusy() argument
1183 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterBusBusy()
1188 if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) in I2CMasterBusBusy()
1237 I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) in I2CMasterControl() argument
1242 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterControl()
1269 HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; in I2CMasterControl()
1287 I2CMasterErr(uint32_t ui32Base) in I2CMasterErr() argument
1294 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterErr()
1299 ui32Err = HWREG(ui32Base + I2C_O_MCS); in I2CMasterErr()
1336 I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) in I2CMasterDataPut() argument
1341 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterDataPut()
1346 HWREG(ui32Base + I2C_O_MDR) = ui8Data; in I2CMasterDataPut()
1362 I2CMasterDataGet(uint32_t ui32Base) in I2CMasterDataGet() argument
1367 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterDataGet()
1372 return(HWREG(ui32Base + I2C_O_MDR)); in I2CMasterDataGet()
1393 I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) in I2CMasterTimeoutSet() argument
1398 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterTimeoutSet()
1403 HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; in I2CMasterTimeoutSet()
1421 I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) in I2CSlaveACKOverride() argument
1426 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveACKOverride()
1433 HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; in I2CSlaveACKOverride()
1437 HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; in I2CSlaveACKOverride()
1456 I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) in I2CSlaveACKValueSet() argument
1461 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveACKValueSet()
1468 HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; in I2CSlaveACKValueSet()
1472 HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; in I2CSlaveACKValueSet()
1510 I2CSlaveStatus(uint32_t ui32Base) in I2CSlaveStatus() argument
1515 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveStatus()
1520 return(HWREG(ui32Base + I2C_O_SCSR)); in I2CSlaveStatus()
1536 I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) in I2CSlaveDataPut() argument
1541 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveDataPut()
1546 HWREG(ui32Base + I2C_O_SDR) = ui8Data; in I2CSlaveDataPut()
1562 I2CSlaveDataGet(uint32_t ui32Base) in I2CSlaveDataGet() argument
1567 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveDataGet()
1572 return(HWREG(ui32Base + I2C_O_SDR)); in I2CSlaveDataGet()
1602 I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) in I2CTxFIFOConfigSet() argument
1607 ASSERT(_I2CBaseValid(ui32Base)); in I2CTxFIFOConfigSet()
1612 HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; in I2CTxFIFOConfigSet()
1617 HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; in I2CTxFIFOConfigSet()
1633 I2CTxFIFOFlush(uint32_t ui32Base) in I2CTxFIFOFlush() argument
1638 ASSERT(_I2CBaseValid(ui32Base)); in I2CTxFIFOFlush()
1643 HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; in I2CTxFIFOFlush()
1672 I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) in I2CRxFIFOConfigSet() argument
1677 ASSERT(_I2CBaseValid(ui32Base)); in I2CRxFIFOConfigSet()
1682 HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; in I2CRxFIFOConfigSet()
1687 HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; in I2CRxFIFOConfigSet()
1702 I2CRxFIFOFlush(uint32_t ui32Base) in I2CRxFIFOFlush() argument
1707 ASSERT(_I2CBaseValid(ui32Base)); in I2CRxFIFOFlush()
1712 HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; in I2CRxFIFOFlush()
1732 I2CFIFOStatus(uint32_t ui32Base) in I2CFIFOStatus() argument
1737 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFOStatus()
1742 return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); in I2CFIFOStatus()
1760 I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) in I2CFIFODataPut() argument
1765 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataPut()
1770 while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) in I2CFIFODataPut()
1777 HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; in I2CFIFODataPut()
1794 I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) in I2CFIFODataPutNonBlocking() argument
1799 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataPutNonBlocking()
1804 if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) in I2CFIFODataPutNonBlocking()
1810 HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; in I2CFIFODataPutNonBlocking()
1829 I2CFIFODataGet(uint32_t ui32Base) in I2CFIFODataGet() argument
1834 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataGet()
1839 while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) in I2CFIFODataGet()
1846 return(HWREG(ui32Base + I2C_O_FIFODATA)); in I2CFIFODataGet()
1864 I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) in I2CFIFODataGetNonBlocking() argument
1869 ASSERT(_I2CBaseValid(ui32Base)); in I2CFIFODataGetNonBlocking()
1874 if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) in I2CFIFODataGetNonBlocking()
1880 *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); in I2CFIFODataGetNonBlocking()
1903 I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) in I2CMasterBurstLengthSet() argument
1908 ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255)); in I2CMasterBurstLengthSet()
1913 HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; in I2CMasterBurstLengthSet()
1931 I2CMasterBurstCountGet(uint32_t ui32Base) in I2CMasterBurstCountGet() argument
1936 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterBurstCountGet()
1941 return(HWREG(ui32Base + I2C_O_MBCNT)); in I2CMasterBurstCountGet()
1972 I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) in I2CMasterGlitchFilterConfigSet() argument
1977 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterGlitchFilterConfigSet()
1982 HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; in I2CMasterGlitchFilterConfigSet()
2009 I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) in I2CSlaveFIFOEnable() argument
2014 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveFIFOEnable()
2019 HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; in I2CSlaveFIFOEnable()
2035 I2CSlaveFIFODisable(uint32_t ui32Base) in I2CSlaveFIFODisable() argument
2040 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveFIFODisable()
2045 HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; in I2CSlaveFIFODisable()