84 static uint_fast16_t getPowerMgrId(uint32_t baseAddr);
244     UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | UART_INT_OE |  in UART2CC32XX_close()
248     uartDmaDisable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX);  in UART2CC32XX_close()
249     MAP_UARTDisable(hwAttrs->baseAddr);  in UART2CC32XX_close()
309     MAP_UARTRxErrorClear(hwAttrs->baseAddr);  in UART2CC32XX_flushRx()
312     while (((int32_t)MAP_UARTCharGetNonBlocking(hwAttrs->baseAddr)) != -1);  in UART2CC32XX_flushRx()
330     status = MAP_UARTIntStatus(hwAttrs->baseAddr, true);  in UART2CC32XX_hwiIntFxn()
331     MAP_UARTIntClear(hwAttrs->baseAddr, status);  in UART2CC32XX_hwiIntFxn()
336             UARTDMADisable(hwAttrs->baseAddr, UART_DMA_RX);  in UART2CC32XX_hwiIntFxn()
343         errStatus = UARTRxErrorGet(hwAttrs->baseAddr);  in UART2CC32XX_hwiIntFxn()
371         UARTDMADisable(hwAttrs->baseAddr, UART_DMA_RX);  in UART2CC32XX_hwiIntFxn()
373         errStatus = MAP_UARTRxErrorGet(hwAttrs->baseAddr);  in UART2CC32XX_hwiIntFxn()
375         MAP_UARTRxErrorClear(hwAttrs->baseAddr);  in UART2CC32XX_hwiIntFxn()
377         UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMARX);  in UART2CC32XX_hwiIntFxn()
378         UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX);  in UART2CC32XX_hwiIntFxn()
400         UARTDMADisable(hwAttrs->baseAddr, UART_DMA_TX);  in UART2CC32XX_hwiIntFxn()
402         UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMATX);  in UART2CC32XX_hwiIntFxn()
403         UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX);  in UART2CC32XX_hwiIntFxn()
499     object->powerMgrId = getPowerMgrId(hwAttrs->baseAddr);  in UART2CC32XX_open()
629     errStatus = UARTRxErrorGet(hwAttrs->baseAddr);  in UART2CC32XX_read()
631     UARTRxErrorClear(hwAttrs->baseAddr);  in UART2CC32XX_read()
656             data = UARTCharGetNonBlocking(hwAttrs->baseAddr);  in UART2CC32XX_read()
812             if (!UARTCharPutNonBlocking(hwAttrs->baseAddr, *buf)) {  in UART2CC32XX_write()
836             UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX);  in UART2CC32XX_write()
837             UARTIntClear(hwAttrs->baseAddr, UART_INT_TX);  in UART2CC32XX_write()
866     uartDmaDisable(hwAttrs->baseAddr, UART_DMA_TX);  in UART2CC32XX_writeCancel()
868     UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMATX);  in UART2CC32XX_writeCancel()
869     UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX);  in UART2CC32XX_writeCancel()
919                                (void *)(hwAttrs->baseAddr + UART_O_DR),  in configDmaRx()
923     uartDmaEnable(hwAttrs->baseAddr, UART_DMA_RX);  in configDmaRx()
925     MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMARX);  in configDmaRx()
953                                (void *)(hwAttrs->baseAddr + UART_O_DR), txSize);  in configDmaTx()
955     uartDmaEnable(hwAttrs->baseAddr, UART_DMA_TX);  in configDmaTx()
957     MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMATX);  in configDmaTx()
967 static uint_fast16_t getPowerMgrId(uint32_t baseAddr)  in getPowerMgrId()  argument
969     switch (baseAddr) {  in getPowerMgrId()
990     MAP_UARTConfigSetExpClk(hwAttrs->baseAddr, freq.lo, object->baudRate,  in initHw()
996     UARTIntClear(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE |  in initHw()
1000     UARTEnable(hwAttrs->baseAddr);  in initHw()
1002     UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | UART_INT_OE |  in initHw()
1005     MAP_UARTFIFOLevelSet(hwAttrs->baseAddr, txFifoThreshold[hwAttrs->txIntFifoThr],  in initHw()
1018     MAP_UARTFlowControlSet(hwAttrs->baseAddr, mode);  in initHw()
1070     uartDmaDisable(hwAttrs->baseAddr, UART_DMA_RX);  in cancelDmaRx()
1072     UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMARX);  in cancelDmaRx()
1073     UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX);  in cancelDmaRx()
1109         data = UARTCharGetNonBlocking(hwAttrs->baseAddr);  in readData()