140         I2CFIFODataPutNonBlocking(hwAttrs->baseAddr, *(object->writeBuf))) {  in I2CCC32XX_fillTransmitFifo()
147     I2CMasterIntClearEx(hwAttrs->baseAddr, I2C_MASTER_INT_TX_FIFO_EMPTY);  in I2CCC32XX_fillTransmitFifo()
171     MAP_I2CMasterIntDisableEx(hwAttrs->baseAddr, 0xFFFFFFFF);  in I2CCC32XX_initHw()
177     MAP_I2CMasterInitExpClk(hwAttrs->baseAddr, freq.lo,  in I2CCC32XX_initHw()
181     MAP_I2CTxFIFOFlush(hwAttrs->baseAddr);  in I2CCC32XX_initHw()
182     MAP_I2CRxFIFOFlush(hwAttrs->baseAddr);  in I2CCC32XX_initHw()
185     MAP_I2CTxFIFOConfigSet(hwAttrs->baseAddr, I2C_FIFO_CFG_TX_MASTER);  in I2CCC32XX_initHw()
186     MAP_I2CRxFIFOConfigSet(hwAttrs->baseAddr, I2C_FIFO_CFG_RX_MASTER);  in I2CCC32XX_initHw()
189     MAP_I2CMasterIntClearEx(hwAttrs->baseAddr, 0xFFFFFFFF);  in I2CCC32XX_initHw()
218     I2CMasterIntDisableEx(hwAttrs->baseAddr, 0xFFFFFFFF);  in I2CCC32XX_completeTransfer()
219     I2CMasterIntClearEx(hwAttrs->baseAddr, 0xFFFFFFFF);  in I2CCC32XX_completeTransfer()
307     intStatus = I2CMasterIntStatusEx(hwAttrs->baseAddr, true);  in I2CCC32XX_hwiFxn()
308     I2CMasterIntClearEx(hwAttrs->baseAddr, intStatus);  in I2CCC32XX_hwiFxn()
313         uint32_t status = HWREG(hwAttrs->baseAddr + I2C_O_MCS);  in I2CCC32XX_hwiFxn()
341             HWREG(hwAttrs->baseAddr + I2C_O_MCS) = I2C_MCS_STOP;  in I2CCC32XX_hwiFxn()
362             I2CMasterIntDisableEx(hwAttrs->baseAddr,  in I2CCC32XX_hwiFxn()
370        !(HWREG(hwAttrs->baseAddr + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)) {  in I2CCC32XX_hwiFxn()
387             uint32_t fifoStatus = I2CFIFOStatus(hwAttrs->baseAddr) &  in I2CCC32XX_hwiFxn()
410     I2CMasterSlaveAddrSet(hwAttrs->baseAddr,  in I2CCC32XX_primeReadBurst()
430         I2CCC32XX_updateReg(hwAttrs->baseAddr + I2C_O_FIFOCTL,  in I2CCC32XX_primeReadBurst()
434         I2CCC32XX_updateReg(hwAttrs->baseAddr + I2C_O_FIFOCTL,  in I2CCC32XX_primeReadBurst()
438     I2CMasterBurstLengthSet(hwAttrs->baseAddr, object->burstCount);  in I2CCC32XX_primeReadBurst()
455     I2CMasterIntEnableEx(hwAttrs->baseAddr, I2C_MASTER_INT_RX_FIFO_REQ |  in I2CCC32XX_primeReadBurst()
458     HWREG(hwAttrs->baseAddr + I2C_O_MCS) = command;  in I2CCC32XX_primeReadBurst()
470     I2CMasterSlaveAddrSet(hwAttrs->baseAddr,  in I2CCC32XX_primeWriteBurst()
482     I2CMasterBurstLengthSet(hwAttrs->baseAddr,  in I2CCC32XX_primeWriteBurst()
503     I2CMasterIntEnableEx(hwAttrs->baseAddr, I2C_MASTER_INT_TX_FIFO_EMPTY  in I2CCC32XX_primeWriteBurst()
507     HWREG(hwAttrs->baseAddr + I2C_O_MCS) = command;  in I2CCC32XX_primeWriteBurst()
538     I2CTxFIFOFlush(hwAttrs->baseAddr);  in I2CCC32XX_primeTransfer()
539     I2CRxFIFOFlush(hwAttrs->baseAddr);  in I2CCC32XX_primeTransfer()
542     if (I2CMasterBusBusy(hwAttrs->baseAddr))  in I2CCC32XX_primeTransfer()
567         I2CFIFODataGetNonBlocking(hwAttrs->baseAddr, object->readBuf)) {  in I2CCC32XX_readRecieveFifo()
573     I2CMasterIntClearEx(hwAttrs->baseAddr, I2C_MASTER_INT_RX_FIFO_REQ);  in I2CCC32XX_readRecieveFifo()
607     MAP_I2CMasterControl(hwAttrs->baseAddr, I2C_MASTER_CMD_BURST_SEND_FINISH);  in I2CCC32XX_cancel()
628     MAP_I2CMasterIntDisableEx(hwAttrs->baseAddr, I2CCC32XX_TRANSFER_INTS);  in I2CCC32XX_close()
631     MAP_I2CMasterDisable(hwAttrs->baseAddr);  in I2CCC32XX_close()
708     MAP_I2CMasterDisable(hwAttrs->baseAddr);  in I2CCC32XX_open()