Lines Matching refs:baseAddress
558 void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress, in EUSCI_B_SPI_select4PinFunctionality() argument
567 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0 in EUSCI_B_SPI_select4PinFunctionality()
585 void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress, in EUSCI_B_SPI_masterChangeClock() argument
589 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_B_SPI_masterChangeClock()
591 EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency in EUSCI_B_SPI_masterChangeClock()
595 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; in EUSCI_B_SPI_masterChangeClock()
633 bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, in EUSCI_B_SPI_slaveInit() argument
657 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_B_SPI_slaveInit()
660 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0 in EUSCI_B_SPI_slaveInit()
689 void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress, in EUSCI_B_SPI_changeClockPhasePolarity() argument
705 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_B_SPI_changeClockPhasePolarity()
707 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0 in EUSCI_B_SPI_changeClockPhasePolarity()
711 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; in EUSCI_B_SPI_changeClockPhasePolarity()
727 void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData) in EUSCI_B_SPI_transmitData() argument
729 EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData; in EUSCI_B_SPI_transmitData()
744 uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress) in EUSCI_B_SPI_receiveData() argument
746 return EUSCI_B_CMSIS(baseAddress)->RXBUF; in EUSCI_B_SPI_receiveData()
768 void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask) in EUSCI_B_SPI_enableInterrupt() argument
775 EUSCI_B_CMSIS(baseAddress)->IE |= mask; in EUSCI_B_SPI_enableInterrupt()
797 void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask) in EUSCI_B_SPI_disableInterrupt() argument
804 EUSCI_B_CMSIS(baseAddress)->IE &= ~mask; in EUSCI_B_SPI_disableInterrupt()
826 uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask) in EUSCI_B_SPI_getInterruptStatus() argument
833 return EUSCI_B_CMSIS(baseAddress)->IFG & mask; in EUSCI_B_SPI_getInterruptStatus()
851 void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask) in EUSCI_B_SPI_clearInterruptFlag() argument
858 EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask; in EUSCI_B_SPI_clearInterruptFlag()
874 void EUSCI_B_SPI_enable(uint32_t baseAddress) in EUSCI_B_SPI_enable() argument
877 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; in EUSCI_B_SPI_enable()
893 void EUSCI_B_SPI_disable(uint32_t baseAddress) in EUSCI_B_SPI_disable() argument
896 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_B_SPI_disable()
911 uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress) in EUSCI_B_SPI_getReceiveBufferAddressForDMA() argument
913 return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF)); in EUSCI_B_SPI_getReceiveBufferAddressForDMA()
928 uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress) in EUSCI_B_SPI_getTransmitBufferAddressForDMA() argument
930 return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF)); in EUSCI_B_SPI_getTransmitBufferAddressForDMA()
945 bool EUSCI_B_SPI_isBusy(uint32_t baseAddress) in EUSCI_B_SPI_isBusy() argument
948 return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS); in EUSCI_B_SPI_isBusy()
969 void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress, in EUSCI_A_SPI_select4PinFunctionality() argument
978 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0 in EUSCI_A_SPI_select4PinFunctionality()
996 void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress, in EUSCI_A_SPI_masterChangeClock() argument
1000 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_A_SPI_masterChangeClock()
1002 EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency in EUSCI_A_SPI_masterChangeClock()
1006 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; in EUSCI_A_SPI_masterChangeClock()
1044 bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, in EUSCI_A_SPI_slaveInit() argument
1068 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_A_SPI_slaveInit()
1071 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0 in EUSCI_A_SPI_slaveInit()
1100 void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress, in EUSCI_A_SPI_changeClockPhasePolarity() argument
1116 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_A_SPI_changeClockPhasePolarity()
1118 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0 in EUSCI_A_SPI_changeClockPhasePolarity()
1122 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; in EUSCI_A_SPI_changeClockPhasePolarity()
1138 void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData) in EUSCI_A_SPI_transmitData() argument
1140 EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData; in EUSCI_A_SPI_transmitData()
1155 uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress) in EUSCI_A_SPI_receiveData() argument
1157 return EUSCI_A_CMSIS(baseAddress)->RXBUF; in EUSCI_A_SPI_receiveData()
1179 void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask) in EUSCI_A_SPI_enableInterrupt() argument
1186 EUSCI_A_CMSIS(baseAddress)->IE |= mask; in EUSCI_A_SPI_enableInterrupt()
1208 void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask) in EUSCI_A_SPI_disableInterrupt() argument
1215 EUSCI_A_CMSIS(baseAddress)->IE &= ~mask; in EUSCI_A_SPI_disableInterrupt()
1237 uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask) in EUSCI_A_SPI_getInterruptStatus() argument
1244 return EUSCI_A_CMSIS(baseAddress)->IFG & mask; in EUSCI_A_SPI_getInterruptStatus()
1262 void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask) in EUSCI_A_SPI_clearInterruptFlag() argument
1269 EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask; in EUSCI_A_SPI_clearInterruptFlag()
1285 void EUSCI_A_SPI_enable(uint32_t baseAddress) in EUSCI_A_SPI_enable() argument
1288 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; in EUSCI_A_SPI_enable()
1304 void EUSCI_A_SPI_disable(uint32_t baseAddress) in EUSCI_A_SPI_disable() argument
1307 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_A_SPI_disable()
1322 uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress) in EUSCI_A_SPI_getReceiveBufferAddressForDMA() argument
1324 return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF; in EUSCI_A_SPI_getReceiveBufferAddressForDMA()
1339 uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress) in EUSCI_A_SPI_getTransmitBufferAddressForDMA() argument
1341 return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF; in EUSCI_A_SPI_getTransmitBufferAddressForDMA()
1355 bool EUSCI_A_SPI_isBusy(uint32_t baseAddress) in EUSCI_A_SPI_isBusy() argument
1358 return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS); in EUSCI_A_SPI_isBusy()