Lines Matching refs:reg_ana_ctrl
112 reg_ana_ctrl = FLD_ANA_CYC; in analog_read_reg8()
130 reg_ana_ctrl = (FLD_ANA_CYC | FLD_ANA_RW); in analog_write_reg8()
132 reg_ana_ctrl =0x00; in analog_write_reg8()
147 reg_ana_ctrl = (FLD_ANA_CYC | FLD_ANA_RW); in analog_write_reg16()
162 reg_ana_ctrl = FLD_ANA_CYC; in analog_read_reg16()
181 reg_ana_ctrl = FLD_ANA_CYC; in analog_read_reg32()
200 reg_ana_ctrl = (FLD_ANA_CYC | FLD_ANA_RW); in analog_write_reg32()
217 reg_ana_ctrl = FLD_ANA_CYC; in analog_read_reg32_dma()
247 reg_ana_ctrl = FLD_ANA_CYC | FLD_ANA_RW; in analog_write_reg32_dma()
275 reg_ana_ctrl = FLD_ANA_CYC | FLD_ANA_RW; in analog_write_buff()
282 reg_ana_ctrl = FLD_ANA_CYC | FLD_ANA_RW; in analog_write_buff()
296 reg_ana_ctrl = 0x00; in analog_write_buff()
314 reg_ana_ctrl = FLD_ANA_CYC; in analog_read_buff()
335 reg_ana_ctrl = 0x00; in analog_read_buff()
358 reg_ana_ctrl = 0x60; in analog_write_buff_dma()
389 reg_ana_ctrl = FLD_ANA_CYC; in analog_read_buff_dma()
424 reg_ana_ctrl = FLD_ANA_RW; in analog_write_addr_data_dma()
428 reg_ana_ctrl = 0x00; in analog_write_addr_data_dma()
442 while(reg_ana_ctrl & FLD_ANA_BUSY){} in analog_wait()