Lines Matching refs:CCER
496 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
502 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
529 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
585 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
594 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
635 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
769 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
772 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
820 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
848 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
851 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
899 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
927 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
930 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
978 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
1006 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); in OC4Config()
1009 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
1048 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1075 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); in OC5Config()
1078 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1109 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1136 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); in OC6Config()
1139 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1169 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()
1192 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; in IC1Config()
1200 MODIFY_REG(TIMx->CCER, in IC1Config()
1225 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; in IC2Config()
1233 MODIFY_REG(TIMx->CCER, in IC2Config()
1258 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; in IC3Config()
1266 MODIFY_REG(TIMx->CCER, in IC3Config()
1291 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; in IC4Config()
1299 MODIFY_REG(TIMx->CCER, in IC4Config()