Lines Matching refs:PWR
34 #if defined(PWR)
214 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
215 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
216 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
217 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
311 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
318 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
344 SET_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_EnterLowPowerRunMode()
354 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_ExitLowPowerRunMode()
364 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); in LL_PWR_IsEnabledLowPowerRunMode()
381 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
393 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); in LL_PWR_GetRegulVoltageScaling()
403 SET_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_EnableBkUpAccess()
413 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_DisableBkUpAccess()
423 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
439 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); in LL_PWR_SetPowerMode()
454 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
468 WRITE_REG(PWR->CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE); in LL_PWR_SetFlashPowerModeLPRun()
471 MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode); in LL_PWR_SetFlashPowerModeLPRun()
483 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDR)); in LL_PWR_GetFlashPowerModeLPRun()
496 MODIFY_REG(PWR->CR1, PWR_CR1_FPDS, FlashLowPowerMode); in LL_PWR_SetFlashPowerModeSleep()
508 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS)); in LL_PWR_GetFlashPowerModeSleep()
520 SET_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_EnablePVM()
532 CLEAR_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_DisablePVM()
544 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVM()
563 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
581 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); in LL_PWR_GetPVDLevel()
591 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
601 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
611 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
625 MODIFY_REG(PWR->CR5, PWR_CR5_RFEOLEN, RadioEOL); in LL_PWR_SetRadioEOL()
637 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_RFEOLEN)); in LL_PWR_GetRadioEOL()
647 SET_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_EnableInternWU()
657 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_DisableInternWU()
667 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL); in LL_PWR_IsEnabledInternWU()
677 SET_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_EnablePUPDCfg()
687 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_DisablePUPDCfg()
697 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDCfg()
707 SET_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_EnableSRAM2Retention()
717 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAM2Retention()
727 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAM2Retention()
739 SET_BIT(PWR->CR3, PWR_CR3_EWPVD); in LL_PWR_EnableWPVD()
749 CLEAR_BIT(PWR->CR3, PWR_CR3_EWPVD); in LL_PWR_DisableWPVD()
759 return ((READ_BIT(PWR->CR3, PWR_CR3_EWPVD) == (PWR_CR3_EWPVD)) ? 1UL : 0UL); in LL_PWR_IsEnabledWPVD()
773 SET_BIT(PWR->CR3, PWR_CR3_ULPEN); in LL_PWR_EnableBORPVD_ULP()
784 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPEN); in LL_PWR_DisableBORPVD_ULP()
795 return ((READ_BIT(PWR->CR3, PWR_CR3_ULPEN) == (PWR_CR3_ULPEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBORPVD_ULP()
811 SET_BIT(PWR->CR3, WakeUpPin); in LL_PWR_EnableWakeUpPin()
827 CLEAR_BIT(PWR->CR3, WakeUpPin); in LL_PWR_DisableWakeUpPin()
843 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
856 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
868 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); in LL_PWR_GetBattChargResistor()
878 SET_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_EnableBatteryCharging()
888 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_DisableBatteryCharging()
898 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
914 SET_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityLow()
930 CLEAR_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityHigh()
946 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsWakeUpPinPolarityLow()
1186 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, OperatingMode); in LL_PWR_SMPS_SetMode()
1198 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSEN)); in LL_PWR_SMPS_GetMode()
1217 …return (uint32_t)(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSRDY_Pos… in LL_PWR_SMPS_GetEffectiveMode()
1230 SET_BIT(PWR->CR5, PWR_CR5_SMPSEN); in LL_PWR_SMPS_Enable()
1243 CLEAR_BIT(PWR->CR5, PWR_CR5_SMPSEN); in LL_PWR_SMPS_Disable()
1253 return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) == (PWR_CR5_SMPSEN)) ? 1UL : 0UL); in LL_PWR_SMPS_IsEnabled()
1274 MODIFY_REG(PWR->CR4, PWR_CR4_WRFBUSYP, RadioBusyPolarity); in LL_PWR_SetRadioBusyPolarity()
1286 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_WRFBUSYP)); in LL_PWR_GetRadioBusyPolarity()
1302 MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger); in LL_PWR_SetRadioBusyTrigger()
1315 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_EWRFBUSY)); in LL_PWR_GetRadioBusyTrigger()
1329 MODIFY_REG(PWR->CR3, PWR_CR3_EWRFIRQ, RadioIRQTrigger); in LL_PWR_SetRadioIRQTrigger()
1342 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_EWRFIRQ)); in LL_PWR_GetRadioIRQTrigger()
1355 MODIFY_REG(PWR->CR1, PWR_CR1_SUBGHZSPINSSSEL, RadioSPI_NSSSource); in LL_PWR_SetSUBGHZSPI_NSSSource()
1367 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SUBGHZSPINSSSEL)); in LL_PWR_GetSUBGHZSPI_NSSSource()
1377 SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); in LL_PWR_UnselectSUBGHZSPI_NSS()
1387 CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); in LL_PWR_SelectSUBGHZSPI_NSS()
1397 return ((READ_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS) != (PWR_SUBGHZSPICR_NSS)) ? 1UL : 0UL); in LL_PWR_IsSUBGHZSPI_NSS_Selected()
1422 MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFBUSY, RadioBusyTrigger); in LL_C2_PWR_SetRadioBusyTrigger()
1436 return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFBUSY)); in LL_C2_PWR_GetRadioBusyTrigger()
1450 MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFIRQ, RadioIRQTrigger); in LL_C2_PWR_SetRadioIRQTrigger()
1463 return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFIRQ)); in LL_C2_PWR_GetRadioIRQTrigger()
1484 SET_BIT(PWR->CR4, PWR_CR4_C2BOOT); in LL_PWR_EnableBootC2()
1495 CLEAR_BIT(PWR->CR4, PWR_CR4_C2BOOT); in LL_PWR_DisableBootC2()
1509 return ((READ_BIT(PWR->CR4, PWR_CR4_C2BOOT) == (PWR_CR4_C2BOOT)) ? 1UL : 0UL); in LL_PWR_IsEnabledBootC2()
1533 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode); in LL_C2_PWR_SetPowerMode()
1548 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_LPMS)); in LL_C2_PWR_GetPowerMode()
1562 WRITE_REG(PWR->C2CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE); in LL_C2_PWR_SetFlashPowerModeLPRun()
1565 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode); in LL_C2_PWR_SetFlashPowerModeLPRun()
1577 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDR)); in LL_C2_PWR_GetFlashPowerModeLPRun()
1590 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDS, FlashLowPowerMode); in LL_C2_PWR_SetFlashPowerModeSleep()
1602 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDS)); in LL_C2_PWR_GetFlashPowerModeSleep()
1613 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_EnableInternWU()
1623 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_DisableInternWU()
1633 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledInternWU()
1649 SET_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_EnableWakeUpPin()
1665 CLEAR_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_DisableWakeUpPin()
1681 return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledWakeUpPin()
1691 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC); in LL_C2_PWR_EnablePUPDCfg()
1701 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC); in LL_C2_PWR_DisablePUPDCfg()
1711 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledPUPDCfg()
1723 SET_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD); in LL_C2_PWR_EnableWPVD()
1733 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD); in LL_C2_PWR_DisableWPVD()
1743 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD) == (PWR_C2CR3_EWPVD)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledWPVD()
1754 SET_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA); in LL_PWR_C2_EnableWakeUp_ILAC()
1765 CLEAR_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA); in LL_PWR_C2_DisableWakeUp_ILAC()
1777 return ((READ_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA) == (PWR_SECCFGR_C2EWILA)) ? 1UL : 0UL); in LL_PWR_C2_IsEnabledWakeUp_ILAC()
1796 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_InternWU()
1806 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1816 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1826 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1836 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); in LL_PWR_ClearFlag_WU()
1846 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); in LL_PWR_ClearFlag_WU3()
1856 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); in LL_PWR_ClearFlag_WU2()
1866 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); in LL_PWR_ClearFlag_WU1()
1876 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO3()
1886 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1896 return ((READ_BIT(PWR->SR2, PWR_SR2_RFEOLF) == (PWR_SR2_RFEOLF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_RFEOL()
1908 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
1918 return ((READ_BIT(PWR->SR1, PWR_SR1_WPVDF) == (PWR_SR1_WPVDF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WPVD()
1928 WRITE_REG(PWR->SCR, PWR_SCR_CWPVDF); in LL_PWR_ClearFlag_WPVD()
1938 return ((READ_BIT(PWR->SR2, PWR_SR2_LDORDY) == (PWR_SR2_LDORDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_LDORDY()
1949 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPF()
1964 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPS()
1976 return ((READ_BIT(PWR->SR2, PWR_SR2_REGMRS) == (PWR_SR2_REGMRS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGMRS()
1986 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASHRDY) == (PWR_SR2_FLASHRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_FLASHRDY()
2004 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) == (PWR_SR2_SMPSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SMPSRDY()
2027 return ((READ_BIT(PWR->SR1, PWR_SR1_WRFBUSYF) == (PWR_SR1_WRFBUSYF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_RFBUSY()
2037 WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF); in LL_PWR_ClearFlag_RFBUSY()
2050 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_RFBUSYS()
2063 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_RFBUSYMS()
2084 return ((READ_BIT(PWR->SR1, PWR_SR1_C2HF) == (PWR_SR1_C2HF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2H()
2095 return ((READ_BIT(PWR->SR2, PWR_SR2_C2BOOTS) == (PWR_SR2_C2BOOTS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2BOOTS()
2106 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOPF) == (PWR_EXTSCR_C1STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C1STOP()
2116 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOP2F) == (PWR_EXTSCR_C1STOP2F)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C1STOP2()
2126 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1SBF) == (PWR_EXTSCR_C1SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C1SB()
2136 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1DS) == (PWR_EXTSCR_C1DS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C1DS()
2147 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOPF) == (PWR_EXTSCR_C2STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2STOP()
2157 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOP2F) == (PWR_EXTSCR_C2STOP2F)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2STOP2()
2167 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2SBF) == (PWR_EXTSCR_C2SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2SB()
2177 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2DS) == (PWR_EXTSCR_C2DS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2DS()
2187 WRITE_REG(PWR->SCR, PWR_SCR_CC2HF); in LL_PWR_ClearFlag_C2H()
2198 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF); in LL_PWR_ClearFlag_C1STOP_C1STB()
2209 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF); in LL_PWR_ClearFlag_C2STOP_C2STB()
2229 SET_BIT(PWR->CR3, PWR_CR3_EC2H); in LL_PWR_EnableIT_HoldCPU2()
2239 CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H); in LL_PWR_DisableIT_HoldCPU2()
2249 return ((READ_BIT(PWR->CR3, PWR_CR3_EC2H) == (PWR_CR3_EC2H)) ? 1UL : 0UL); in LL_PWR_IsEnabledIT_HoldCPU2()