500   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
506   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
533   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
589   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
598   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
639   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
770   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
773   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
823   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
849   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
852   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
902   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
928   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
931   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
981   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1007   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1010   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1048   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1075   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1078   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1109   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1136   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1139   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1169   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1192   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1200   MODIFY_REG(TIMx->CCER,  in IC1Config()
1225   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1233   MODIFY_REG(TIMx->CCER,  in IC2Config()
1258   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1266   MODIFY_REG(TIMx->CCER,  in IC3Config()
1291   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1299   MODIFY_REG(TIMx->CCER,  in IC4Config()