Lines Matching refs:hqspi
259 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, F…
260 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod…
290 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Init() argument
296 if(hqspi == NULL) in HAL_QSPI_Init()
302 assert_param(IS_QUADSPI_ALL_INSTANCE(hqspi->Instance)); in HAL_QSPI_Init()
303 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); in HAL_QSPI_Init()
304 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
305 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
306 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); in HAL_QSPI_Init()
307 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); in HAL_QSPI_Init()
308 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); in HAL_QSPI_Init()
310 if(hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_Init()
313 hqspi->Lock = HAL_UNLOCKED; in HAL_QSPI_Init()
317 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_Init()
318 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_Init()
319 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_Init()
320 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_Init()
321 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_Init()
322 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_Init()
323 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_Init()
324 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_Init()
325 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_Init()
326 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_Init()
328 if(hqspi->MspInitCallback == NULL) in HAL_QSPI_Init()
330 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_Init()
334 hqspi->MspInitCallback(hqspi); in HAL_QSPI_Init()
337 HAL_QSPI_MspInit(hqspi); in HAL_QSPI_Init()
341 HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); in HAL_QSPI_Init()
345 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_Init()
346 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
349 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Init()
354 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), in HAL_QSPI_Init()
355 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | in HAL_QSPI_Init()
356 hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
359 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), in HAL_QSPI_Init()
360 ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | in HAL_QSPI_Init()
361 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); in HAL_QSPI_Init()
364 __HAL_QSPI_ENABLE(hqspi); in HAL_QSPI_Init()
367 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Init()
370 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Init()
374 __HAL_UNLOCK(hqspi); in HAL_QSPI_Init()
385 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_DeInit() argument
388 if(hqspi == NULL) in HAL_QSPI_DeInit()
394 __HAL_QSPI_DISABLE(hqspi); in HAL_QSPI_DeInit()
397 if(hqspi->MspDeInitCallback == NULL) in HAL_QSPI_DeInit()
399 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_DeInit()
403 hqspi->MspDeInitCallback(hqspi); in HAL_QSPI_DeInit()
406 HAL_QSPI_MspDeInit(hqspi); in HAL_QSPI_DeInit()
410 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_DeInit()
413 hqspi->State = HAL_QSPI_STATE_RESET; in HAL_QSPI_DeInit()
416 __HAL_UNLOCK(hqspi); in HAL_QSPI_DeInit()
426 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspInit() argument
429 UNUSED(hqspi); in HAL_QSPI_MspInit()
441 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspDeInit() argument
444 UNUSED(hqspi); in HAL_QSPI_MspDeInit()
480 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_IRQHandler() argument
483 uint32_t flag = READ_REG(hqspi->Instance->SR); in HAL_QSPI_IRQHandler()
484 uint32_t itsource = READ_REG(hqspi->Instance->CR); in HAL_QSPI_IRQHandler()
489 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
491 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
494 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
496 if (hqspi->TxXferCount > 0U) in HAL_QSPI_IRQHandler()
499 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_IRQHandler()
500 hqspi->pTxBuffPtr++; in HAL_QSPI_IRQHandler()
501 hqspi->TxXferCount--; in HAL_QSPI_IRQHandler()
507 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
512 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
515 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
517 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
520 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
521 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
522 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
528 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
540 hqspi->FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
542 HAL_QSPI_FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
550 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); in HAL_QSPI_IRQHandler()
553 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
556 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
558 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
561 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
564 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
569 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
573 hqspi->TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
575 HAL_QSPI_TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
578 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
580 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
583 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
586 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
590 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
591 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) in HAL_QSPI_IRQHandler()
593 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
596 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
597 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
598 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
610 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
614 hqspi->RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
616 HAL_QSPI_RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
619 else if(hqspi->State == HAL_QSPI_STATE_BUSY) in HAL_QSPI_IRQHandler()
622 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
626 hqspi->CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
628 HAL_QSPI_CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
631 else if(hqspi->State == HAL_QSPI_STATE_ABORT) in HAL_QSPI_IRQHandler()
634 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_IRQHandler()
637 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
639 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) in HAL_QSPI_IRQHandler()
645 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
647 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
656 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
658 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
672 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); in HAL_QSPI_IRQHandler()
675 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) in HAL_QSPI_IRQHandler()
678 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_IRQHandler()
681 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
686 hqspi->StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
688 HAL_QSPI_StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
696 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); in HAL_QSPI_IRQHandler()
699 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
702 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; in HAL_QSPI_IRQHandler()
704 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
707 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
710 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_IRQHandler()
711 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_IRQHandler()
714 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_IRQHandler()
717 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
721 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
723 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
730 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
734 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
736 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
745 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); in HAL_QSPI_IRQHandler()
749 hqspi->TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
751 HAL_QSPI_TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
769 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Ti… in HAL_QSPI_Command() argument
800 __HAL_LOCK(hqspi); in HAL_QSPI_Command()
802 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command()
804 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command()
807 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command()
810 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_Command()
815 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command()
821 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Command()
825 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Command()
828 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
834 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
844 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command()
857 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) in HAL_QSPI_Command_IT() argument
888 __HAL_LOCK(hqspi); in HAL_QSPI_Command_IT()
890 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command_IT()
892 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command_IT()
895 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command_IT()
898 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Command_IT()
905 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Command_IT()
909 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command_IT()
916 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
919 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); in HAL_QSPI_Command_IT()
924 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command_IT()
927 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
933 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
941 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
956 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Transmit() argument
960 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Transmit()
963 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit()
965 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit()
967 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit()
972 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit()
975 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
976 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
977 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit()
980 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
982 while(hqspi->TxXferCount > 0U) in HAL_QSPI_Transmit()
985 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
992 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_Transmit()
993 hqspi->pTxBuffPtr++; in HAL_QSPI_Transmit()
994 hqspi->TxXferCount--; in HAL_QSPI_Transmit()
1000 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1005 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Transmit()
1011 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit()
1015 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit()
1025 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit()
1039 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Receive() argument
1043 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive()
1044 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Receive()
1047 __HAL_LOCK(hqspi); in HAL_QSPI_Receive()
1049 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive()
1051 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive()
1056 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive()
1059 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1060 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1061 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive()
1064 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
1067 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
1069 while(hqspi->RxXferCount > 0U) in HAL_QSPI_Receive()
1072 …status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Time… in HAL_QSPI_Receive()
1079 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_Receive()
1080 hqspi->pRxBuffPtr++; in HAL_QSPI_Receive()
1081 hqspi->RxXferCount--; in HAL_QSPI_Receive()
1087 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Receive()
1092 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Receive()
1098 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive()
1102 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive()
1112 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive()
1124 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_IT() argument
1129 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_IT()
1131 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_IT()
1133 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_IT()
1138 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_IT()
1141 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1142 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1143 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_IT()
1146 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Transmit_IT()
1149 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
1152 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1155 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Transmit_IT()
1159 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_IT()
1163 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1171 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1184 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_IT() argument
1187 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_IT()
1190 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_IT()
1192 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_IT()
1194 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_IT()
1199 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_IT()
1202 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1203 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1204 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_IT()
1207 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Receive_IT()
1210 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
1213 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1216 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1219 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Receive_IT()
1223 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_IT()
1227 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1235 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1252 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_DMA() argument
1255 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Transmit_DMA()
1258 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1260 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_DMA()
1263 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_DMA()
1268 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Transmit_DMA()
1270 hqspi->TxXferCount = data_size; in HAL_QSPI_Transmit_DMA()
1272 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Transmit_DMA()
1274 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1278 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1282 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1286 hqspi->TxXferCount = (data_size >> 1U); in HAL_QSPI_Transmit_DMA()
1289 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Transmit_DMA()
1291 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1295 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1299 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1303 hqspi->TxXferCount = (data_size >> 2U); in HAL_QSPI_Transmit_DMA()
1314 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_DMA()
1317 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Transmit_DMA()
1320 hqspi->TxXferSize = hqspi->TxXferCount; in HAL_QSPI_Transmit_DMA()
1321 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_DMA()
1324 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1327 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; in HAL_QSPI_Transmit_DMA()
1330 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; in HAL_QSPI_Transmit_DMA()
1333 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Transmit_DMA()
1336 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Transmit_DMA()
1339 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; in HAL_QSPI_Transmit_DMA()
1340 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Transmit_DMA()
1343 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSi… in HAL_QSPI_Transmit_DMA()
1346 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1349 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Transmit_DMA()
1352 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Transmit_DMA()
1357 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Transmit_DMA()
1358 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit_DMA()
1361 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1367 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1371 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1379 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1396 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_DMA() argument
1399 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_DMA()
1400 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Receive_DMA()
1403 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_DMA()
1405 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_DMA()
1408 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_DMA()
1413 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Receive_DMA()
1415 hqspi->RxXferCount = data_size; in HAL_QSPI_Receive_DMA()
1417 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Receive_DMA()
1419 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1423 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1427 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1431 hqspi->RxXferCount = (data_size >> 1U); in HAL_QSPI_Receive_DMA()
1434 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Receive_DMA()
1436 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
1440 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1444 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1448 hqspi->RxXferCount = (data_size >> 2U); in HAL_QSPI_Receive_DMA()
1459 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_DMA()
1462 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Receive_DMA()
1465 hqspi->RxXferSize = hqspi->RxXferCount; in HAL_QSPI_Receive_DMA()
1466 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_DMA()
1469 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; in HAL_QSPI_Receive_DMA()
1472 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; in HAL_QSPI_Receive_DMA()
1475 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Receive_DMA()
1478 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Receive_DMA()
1481 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; in HAL_QSPI_Receive_DMA()
1482 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Receive_DMA()
1485 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSi… in HAL_QSPI_Receive_DMA()
1488 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1491 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1494 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1497 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Receive_DMA()
1500 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Receive_DMA()
1505 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1506 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive_DMA()
1509 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1515 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1519 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1527 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1542 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_Au… in HAL_QSPI_AutoPolling() argument
1577 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling()
1579 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling()
1581 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling()
1584 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling()
1587 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1592 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1595 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1598 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
1602 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling()
1607 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling()
1610 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1614 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); in HAL_QSPI_AutoPolling()
1617 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_AutoPolling()
1627 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling()
1641 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI… in HAL_QSPI_AutoPolling_IT() argument
1677 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1679 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling_IT()
1681 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling_IT()
1684 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling_IT()
1687 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_AutoPolling_IT()
1692 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling_IT()
1695 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling_IT()
1698 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling_IT()
1701 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling_IT()
1705 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); in HAL_QSPI_AutoPolling_IT()
1709 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling_IT()
1712 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1715 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_AutoPolling_IT()
1721 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1729 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1744 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_M… in HAL_QSPI_MemoryMapped() argument
1777 __HAL_LOCK(hqspi); in HAL_QSPI_MemoryMapped()
1779 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_MemoryMapped()
1781 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_MemoryMapped()
1784 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; in HAL_QSPI_MemoryMapped()
1787 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_MemoryMapped()
1792 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); in HAL_QSPI_MemoryMapped()
1799 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); in HAL_QSPI_MemoryMapped()
1802 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); in HAL_QSPI_MemoryMapped()
1805 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); in HAL_QSPI_MemoryMapped()
1809 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); in HAL_QSPI_MemoryMapped()
1818 __HAL_UNLOCK(hqspi); in HAL_QSPI_MemoryMapped()
1829 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_ErrorCallback() argument
1832 UNUSED(hqspi); in HAL_QSPI_ErrorCallback()
1844 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_AbortCpltCallback() argument
1847 UNUSED(hqspi); in HAL_QSPI_AbortCpltCallback()
1859 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_CmdCpltCallback() argument
1862 UNUSED(hqspi); in HAL_QSPI_CmdCpltCallback()
1874 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxCpltCallback() argument
1877 UNUSED(hqspi); in HAL_QSPI_RxCpltCallback()
1889 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxCpltCallback() argument
1892 UNUSED(hqspi); in HAL_QSPI_TxCpltCallback()
1904 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxHalfCpltCallback() argument
1907 UNUSED(hqspi); in HAL_QSPI_RxHalfCpltCallback()
1919 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxHalfCpltCallback() argument
1922 UNUSED(hqspi); in HAL_QSPI_TxHalfCpltCallback()
1934 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_FifoThresholdCallback() argument
1937 UNUSED(hqspi); in HAL_QSPI_FifoThresholdCallback()
1949 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_StatusMatchCallback() argument
1952 UNUSED(hqspi); in HAL_QSPI_StatusMatchCallback()
1964 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TimeOutCallback() argument
1967 UNUSED(hqspi); in HAL_QSPI_TimeOutCallback()
1995 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef … in HAL_QSPI_RegisterCallback() argument
2002 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2007 __HAL_LOCK(hqspi); in HAL_QSPI_RegisterCallback()
2009 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_RegisterCallback()
2014 hqspi->ErrorCallback = pCallback; in HAL_QSPI_RegisterCallback()
2017 hqspi->AbortCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2020 hqspi->FifoThresholdCallback = pCallback; in HAL_QSPI_RegisterCallback()
2023 hqspi->CmdCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2026 hqspi->RxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2029 hqspi->TxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2032 hqspi->RxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2035 hqspi->TxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2038 hqspi->StatusMatchCallback = pCallback; in HAL_QSPI_RegisterCallback()
2041 hqspi->TimeOutCallback = pCallback; in HAL_QSPI_RegisterCallback()
2044 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2047 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2051 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2057 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_RegisterCallback()
2062 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2065 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2069 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2078 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2084 __HAL_UNLOCK(hqspi); in HAL_QSPI_RegisterCallback()
2108 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDe… in HAL_QSPI_UnRegisterCallback() argument
2113 __HAL_LOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2115 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_UnRegisterCallback()
2120 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_UnRegisterCallback()
2123 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_UnRegisterCallback()
2126 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_UnRegisterCallback()
2129 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_UnRegisterCallback()
2132 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2135 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2138 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2141 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2144 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_UnRegisterCallback()
2147 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_UnRegisterCallback()
2150 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2153 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2157 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2163 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_UnRegisterCallback()
2168 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2171 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2175 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2184 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2190 __HAL_UNLOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2222 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetState() argument
2225 return hqspi->State; in HAL_QSPI_GetState()
2233 uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetError() argument
2235 return hqspi->ErrorCode; in HAL_QSPI_GetError()
2243 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort() argument
2249 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort()
2252 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort()
2254 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort()
2257 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort()
2260 status = HAL_DMA_Abort(hqspi->hdma); in HAL_QSPI_Abort()
2263 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Abort()
2267 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort()
2270 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort()
2273 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2277 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort()
2280 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2286 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_Abort()
2289 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2295 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2307 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort_IT() argument
2312 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort_IT()
2315 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort_IT()
2318 hqspi->State = HAL_QSPI_STATE_ABORT; in HAL_QSPI_Abort_IT()
2321 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); in HAL_QSPI_Abort_IT()
2323 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort_IT()
2326 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort_IT()
2329 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_Abort_IT()
2330 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_Abort_IT()
2333 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2337 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2339 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2345 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort_IT()
2348 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort_IT()
2351 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in HAL_QSPI_Abort_IT()
2354 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort_IT()
2359 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2371 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) in HAL_QSPI_SetTimeout() argument
2373 hqspi->Timeout = Timeout; in HAL_QSPI_SetTimeout()
2381 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) in HAL_QSPI_SetFifoThreshold() argument
2386 __HAL_LOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2388 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFifoThreshold()
2391 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2394 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_SetFifoThreshold()
2395 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
2403 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2413 uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetFifoThreshold() argument
2415 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); in HAL_QSPI_GetFifoThreshold()
2437 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxCplt() local
2438 hqspi->RxXferCount = 0U; in QSPI_DMARxCplt()
2441 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMARxCplt()
2451 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxCplt() local
2452 hqspi->TxXferCount = 0U; in QSPI_DMATxCplt()
2455 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMATxCplt()
2465 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxHalfCplt() local
2468 hqspi->RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2470 HAL_QSPI_RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2481 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxHalfCplt() local
2484 hqspi->TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2486 HAL_QSPI_TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2497 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAError() local
2499 hqspi->RxXferCount = 0U; in QSPI_DMAError()
2500 hqspi->TxXferCount = 0U; in QSPI_DMAError()
2501 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in QSPI_DMAError()
2504 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in QSPI_DMAError()
2507 (void)HAL_QSPI_Abort_IT(hqspi); in QSPI_DMAError()
2518 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAAbortCplt() local
2520 hqspi->RxXferCount = 0U; in QSPI_DMAAbortCplt()
2521 hqspi->TxXferCount = 0U; in QSPI_DMAAbortCplt()
2523 if(hqspi->State == HAL_QSPI_STATE_ABORT) in QSPI_DMAAbortCplt()
2527 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in QSPI_DMAAbortCplt()
2530 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMAAbortCplt()
2533 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in QSPI_DMAAbortCplt()
2539 hqspi->State = HAL_QSPI_STATE_READY; in QSPI_DMAAbortCplt()
2543 hqspi->ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2545 HAL_QSPI_ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2559 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, in QSPI_WaitFlagStateUntilTimeout() argument
2563 while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) in QSPI_WaitFlagStateUntilTimeout()
2570 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout()
2571 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout()
2592 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod… in QSPI_Config() argument
2599 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); in QSPI_Config()
2607 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2613 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()
2622 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2629 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()
2642 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()
2650 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2657 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()
2669 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2675 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()
2684 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2691 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()
2703 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()
2711 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2720 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode | in QSPI_Config()