Lines Matching refs:PWR
34 #if defined(PWR)
269 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
270 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
271 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
272 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
273 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
274 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
407 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
414 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
440 SET_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_EnterLowPowerRunMode()
450 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_ExitLowPowerRunMode()
460 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); in LL_PWR_IsEnabledLowPowerRunMode()
478 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
490 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); in LL_PWR_GetRegulVoltageScaling()
501 SET_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_EnableBkUpAccess()
511 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_DisableBkUpAccess()
521 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
539 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); in LL_PWR_SetPowerMode()
556 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
570 WRITE_REG(PWR->CR1, 0x0000C1B0UL); in LL_PWR_SetFlashPowerModeLPRun()
573 MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode); in LL_PWR_SetFlashPowerModeLPRun()
585 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDR)); in LL_PWR_GetFlashPowerModeLPRun()
598 MODIFY_REG(PWR->CR1, PWR_CR1_FPDS, FlashLowPowerMode); in LL_PWR_SetFlashPowerModeSleep()
610 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS)); in LL_PWR_GetFlashPowerModeSleep()
621 SET_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_EnableVddUSB()
631 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_DisableVddUSB()
641 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSB()
658 SET_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_EnablePVM()
674 CLEAR_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_DisablePVM()
690 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVM()
709 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
727 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); in LL_PWR_GetPVDLevel()
737 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
747 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
757 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
767 SET_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_EnableInternWU()
777 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_DisableInternWU()
787 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL); in LL_PWR_IsEnabledInternWU()
797 SET_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_EnablePUPDCfg()
807 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_DisablePUPDCfg()
817 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDCfg()
829 SET_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_EnableSRAM2Retention()
841 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAM2Retention()
853 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAM2Retention()
875 SET_BIT(PWR->CR3, WakeUpPin); in LL_PWR_EnableWakeUpPin()
897 CLEAR_BIT(PWR->CR3, WakeUpPin); in LL_PWR_DisableWakeUpPin()
919 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
932 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
944 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); in LL_PWR_GetBattChargResistor()
954 SET_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_EnableBatteryCharging()
964 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_DisableBatteryCharging()
974 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
996 SET_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityLow()
1018 CLEAR_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityHigh()
1040 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsWakeUpPinPolarityLow()
1295 MODIFY_REG(PWR->CR5, PWR_CR5_BORHC, BORConfiguration); in LL_PWR_SetBORConfig()
1307 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_BORHC)); in LL_PWR_GetBORConfig()
1351 …MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, (OperatingMode & PWR_SR2_SMPSF) << (PWR_CR5_SMPSEN_Pos - PWR_… in LL_PWR_SMPS_SetMode()
1372 …uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPS… in LL_PWR_SMPS_GetMode()
1403 return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF))); in LL_PWR_SMPS_GetEffectiveMode()
1416 SET_BIT(PWR->CR5, PWR_CR5_SMPSEN); in LL_PWR_SMPS_Enable()
1429 CLEAR_BIT(PWR->CR5, PWR_CR5_SMPSEN); in LL_PWR_SMPS_Disable()
1439 return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) == (PWR_CR5_SMPSEN)) ? 1UL : 0UL); in LL_PWR_SMPS_IsEnabled()
1458 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSSC, StartupCurrent); in LL_PWR_SMPS_SetStartupCurrent()
1476 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSSC)); in LL_PWR_SMPS_GetStartupCurrent()
1514 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, OutputVoltageLevel); in LL_PWR_SMPS_SetOutputVoltageLevel()
1537 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, (uint32_t)OutputVoltageLevelTrimmed); in LL_PWR_SMPS_SetOutputVoltageLevel()
1574 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS)); in LL_PWR_SMPS_GetOutputVoltageLevel()
1582 …OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS)) - TrimmingSt… in LL_PWR_SMPS_GetOutputVoltageLevel()
1617 SET_BIT(PWR->CR4, PWR_CR4_C2BOOT); in LL_PWR_EnableBootC2()
1628 CLEAR_BIT(PWR->CR4, PWR_CR4_C2BOOT); in LL_PWR_DisableBootC2()
1639 return ((READ_BIT(PWR->CR4, PWR_CR4_C2BOOT) == (PWR_CR4_C2BOOT)) ? 1UL : 0UL); in LL_PWR_IsEnabledBootC2()
1665 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode); in LL_C2_PWR_SetPowerMode()
1682 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_LPMS)); in LL_C2_PWR_GetPowerMode()
1696 WRITE_REG(PWR->C2CR1, 0x0000C1B0UL); in LL_C2_PWR_SetFlashPowerModeLPRun()
1699 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode); in LL_C2_PWR_SetFlashPowerModeLPRun()
1711 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDR)); in LL_C2_PWR_GetFlashPowerModeLPRun()
1724 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDS, FlashLowPowerMode); in LL_C2_PWR_SetFlashPowerModeSleep()
1736 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDS)); in LL_C2_PWR_GetFlashPowerModeSleep()
1747 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_EnableInternWU()
1757 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); in LL_C2_PWR_DisableInternWU()
1767 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledInternWU()
1789 SET_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_EnableWakeUpPin()
1811 CLEAR_BIT(PWR->C2CR3, WakeUpPin); in LL_C2_PWR_DisableWakeUpPin()
1833 return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledWakeUpPin()
1843 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC); in LL_C2_PWR_EnablePUPDCfg()
1853 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC); in LL_C2_PWR_DisablePUPDCfg()
1863 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledPUPDCfg()
1883 SET_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP); in LL_C2_PWR_WakeUp_BLE()
1894 return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL); in LL_C2_PWR_IsWokenUp_BLE()
1907 SET_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP); in LL_C2_PWR_WakeUp_802_15_4()
1918 return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL); in LL_C2_PWR_IsWokenUp_802_15_4()
1937 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_InternWU()
1948 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
1959 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1970 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1982 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1993 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
2003 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); in LL_PWR_ClearFlag_WU()
2014 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); in LL_PWR_ClearFlag_WU5()
2025 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); in LL_PWR_ClearFlag_WU4()
2036 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); in LL_PWR_ClearFlag_WU3()
2048 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); in LL_PWR_ClearFlag_WU2()
2059 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); in LL_PWR_ClearFlag_WU1()
2070 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO3()
2081 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO1()
2092 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
2103 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
2115 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPF()
2125 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPS()
2135 return ((READ_BIT(PWR->SR1, PWR_SR1_BORHF) == (PWR_SR1_BORHF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BORH()
2145 WRITE_REG(PWR->SCR, PWR_SCR_CBORHF); in LL_PWR_ClearFlag_BORH()
2168 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSFBF) == (PWR_SR1_SMPSFBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SMPSFB()
2182 WRITE_REG(PWR->SCR, PWR_SCR_CSMPSFBF); in LL_PWR_ClearFlag_SMPSFB()
2201 return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BLEWU()
2212 return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_802WU()
2223 return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BLEA()
2234 return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_802A()
2245 return ((READ_BIT(PWR->SR1, PWR_SR1_CRPEF) == (PWR_SR1_CRPEF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_CRPE()
2255 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_CRPF) == (PWR_EXTSCR_CRPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_CRP()
2265 WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF); in LL_PWR_ClearFlag_BLEWU()
2276 WRITE_REG(PWR->SCR, PWR_SCR_C802WUF); in LL_PWR_ClearFlag_802WU()
2287 WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF); in LL_PWR_ClearFlag_BLEA()
2298 WRITE_REG(PWR->SCR, PWR_SCR_C802AF); in LL_PWR_ClearFlag_802A()
2309 WRITE_REG(PWR->SCR, PWR_SCR_CCRPEF); in LL_PWR_ClearFlag_CRPE()
2319 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_CCRPF); in LL_PWR_ClearFlag_CRP()
2337 return ((READ_BIT(PWR->SR1, PWR_SR1_C2HF) == (PWR_SR1_C2HF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2H()
2347 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOPF) == (PWR_EXTSCR_C1STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C1STOP()
2357 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1SBF) == (PWR_EXTSCR_C1SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C1SB()
2367 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1DS) == (PWR_EXTSCR_C1DS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C1DS()
2377 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOPF) == (PWR_EXTSCR_C2STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2STOP()
2387 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2SBF) == (PWR_EXTSCR_C2SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2SB()
2397 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2DS) == (PWR_EXTSCR_C2DS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_C2DS()
2407 WRITE_REG(PWR->SCR, PWR_SCR_CC2HF); in LL_PWR_ClearFlag_C2H()
2416 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF); in LL_PWR_ClearFlag_C1STOP_C1STB()
2426 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF); in LL_PWR_ClearFlag_C2STOP_C2STB()
2450 SET_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB); in LL_PWR_EnableIT_BORH_SMPSFB()
2461 CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB); in LL_PWR_DisableIT_BORH_SMPSFB()
2472 return ((READ_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB) == (PWR_CR3_EBORHSMPSFB)) ? 1UL : 0UL); in LL_PWR_IsEnabledIT_BORH_SMPSFB()
2491 SET_BIT(PWR->CR3, PWR_CR3_EBLEA); in LL_PWR_EnableIT_BLEA()
2502 SET_BIT(PWR->CR3, PWR_CR3_E802A); in LL_PWR_EnableIT_802A()
2513 CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA); in LL_PWR_DisableIT_BLEA()
2524 CLEAR_BIT(PWR->CR3, PWR_CR3_E802A); in LL_PWR_DisableIT_802A()
2535 return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL); in LL_PWR_IsEnabledIT_BLEA()
2546 return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL); in LL_PWR_IsEnabledIT_802A()
2557 SET_BIT(PWR->CR3, PWR_CR3_ECRPE); in LL_PWR_EnableIT_CRPE()
2567 CLEAR_BIT(PWR->CR3, PWR_CR3_ECRPE); in LL_PWR_DisableIT_CRPE()
2577 return ((READ_BIT(PWR->CR3, PWR_CR3_ECRPE) == (PWR_CR3_ECRPE)) ? 1UL : 0UL); in LL_PWR_IsEnabledIT_CRPE()
2595 SET_BIT(PWR->CR3, PWR_CR3_EC2H); in LL_PWR_EnableIT_HoldCPU2()
2605 CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H); in LL_PWR_DisableIT_HoldCPU2()
2615 return ((READ_BIT(PWR->CR3, PWR_CR3_EC2H) == (PWR_CR3_EC2H)) ? 1UL : 0UL); in LL_PWR_IsEnabledIT_HoldCPU2()
2633 SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP); in LL_C2_PWR_EnableIT_BLEWU()
2644 SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); in LL_C2_PWR_EnableIT_802WU()
2655 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP); in LL_C2_PWR_DisableIT_BLEWU()
2666 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); in LL_C2_PWR_DisableIT_802WU()
2677 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledIT_BLEWU()
2688 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL); in LL_C2_PWR_IsEnabledIT_802WU()