590   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
605   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
617   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
620   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
643   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
774   uint32_t tmpcr2;  in OC1Config()  local
789   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
820     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
823     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
827   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
853   uint32_t tmpcr2;  in OC2Config()  local
868   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
899     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
902     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
906   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
932   uint32_t tmpcr2;  in OC3Config()  local
947   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
978     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
981     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
985   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1011   uint32_t tmpcr2;  in OC4Config()  local
1026   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1057     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1060     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);  in OC4Config()
1064   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()