498   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
519   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
534   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
535   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
536   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
537   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
546   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
592   uint32_t tmpccer;  in LL_TIM_HALLSENSOR_Init()  local
611   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
638   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_HALLSENSOR_Init()
639   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);  in LL_TIM_HALLSENSOR_Init()
640   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
652   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
773   uint32_t tmpccer;  in OC1Config()  local
786   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
801   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
804   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
814     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);  in OC1Config()
817     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);  in OC1Config()
836   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
852   uint32_t tmpccer;  in OC2Config()  local
865   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
880   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
883   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
893     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);  in OC2Config()
896     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);  in OC2Config()
915   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
931   uint32_t tmpccer;  in OC3Config()  local
944   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
959   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
962   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
972     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);  in OC3Config()
975     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);  in OC3Config()
994   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1010   uint32_t tmpccer;  in OC4Config()  local
1023   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1038   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
1041   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
1051     MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);  in OC4Config()
1054     MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);  in OC4Config()
1073   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1089   uint32_t tmpccer;  in OC5Config()  local
1103   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1112   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);  in OC5Config()
1115   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);  in OC5Config()
1134   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1150   uint32_t tmpccer;  in OC6Config()  local
1164   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1173   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);  in OC6Config()
1176   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);  in OC6Config()
1194   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()