Lines Matching refs:CCER
513 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
519 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
546 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
602 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
611 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
652 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
783 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
786 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
836 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
862 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
865 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
915 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
941 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
944 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
994 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
1020 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); in OC4Config()
1023 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
1073 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1100 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); in OC5Config()
1103 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1134 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1161 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); in OC6Config()
1164 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1194 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()
1217 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; in IC1Config()
1225 MODIFY_REG(TIMx->CCER, in IC1Config()
1250 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; in IC2Config()
1258 MODIFY_REG(TIMx->CCER, in IC2Config()
1283 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; in IC3Config()
1291 MODIFY_REG(TIMx->CCER, in IC3Config()
1316 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; in IC4Config()
1324 MODIFY_REG(TIMx->CCER, in IC4Config()