Lines Matching refs:PWR
34 #if defined(PWR)
257 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA (uint32_t)(&(PWR->IORETENRA)) /*!< GPIO port A */
258 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB (uint32_t)(&(PWR->IORETENRB)) /*!< GPIO port B */
259 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC (uint32_t)(&(PWR->IORETENRC)) /*!< GPIO port C */
260 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH (uint32_t)(&(PWR->IORETENRH)) /*!< GPIO port H */
268 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA (uint32_t)(&(PWR->IORETRA)) /*!< GPIO port A */
269 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB (uint32_t)(&(PWR->IORETRB)) /*!< GPIO port B */
270 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC (uint32_t)(&(PWR->IORETRC)) /*!< GPIO port C */
271 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH (uint32_t)(&(PWR->IORETRH)) /*!< GPIO port H */
349 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
356 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
386 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode); in LL_PWR_SetPowerMode()
399 return (READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
412 MODIFY_REG(PWR->CR1, PWR_CR1_R2RSB1, SRAM2PageRetention); in LL_PWR_SetSRAM2SBRetention()
424 return (READ_BIT(PWR->CR1, PWR_CR1_R2RSB1)); in LL_PWR_GetSRAM2SBRetention()
437 MODIFY_REG(PWR->CR1, PWR_CR1_R1RSB1, SRAM1PageRetention); in LL_PWR_SetSRAM1SBRetention()
449 return (READ_BIT(PWR->CR1, PWR_CR1_R1RSB1)); in LL_PWR_GetSRAM1SBRetention()
462 MODIFY_REG(PWR->CR1, PWR_CR1_RADIORSB, RadioRetention); in LL_PWR_SetRadioSBRetention()
474 return (READ_BIT(PWR->CR1, PWR_CR1_RADIORSB)); in LL_PWR_GetRadioSBRetention()
484 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); in LL_PWR_EnableUltraLowPowerMode()
494 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); in LL_PWR_DisableUltraLowPowerMode()
504 return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUltraLowPowerMode()
518 MODIFY_REG(PWR->CR2, PWR_CR2_SRAM1PDS1, ((~SRAM1PageRetention) & PWR_CR2_SRAM1PDS1)); in LL_PWR_SetSRAM1StopRetention()
530 return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM1PDS1))) & PWR_CR2_SRAM1PDS1); in LL_PWR_GetSRAM1StopRetention()
543 MODIFY_REG(PWR->CR2, PWR_CR2_SRAM2PDS1, ((~SRAM2PageRetention) & PWR_CR2_SRAM2PDS1)); in LL_PWR_SetSRAM2StopRetention()
555 return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM2PDS1))) & PWR_CR2_SRAM2PDS1); in LL_PWR_GetSRAM2StopRetention()
572 MODIFY_REG(PWR->CR2, PWR_CR2_ICRAMPDS, ((~ICRAMPageRetention) & PWR_CR2_ICRAMPDS)); in LL_PWR_SetICacheRAMStopRetention()
584 return ((~(READ_BIT(PWR->CR2, PWR_CR2_ICRAMPDS))) & PWR_CR2_ICRAMPDS); in LL_PWR_GetICacheRAMStopRetention()
594 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); in LL_PWR_EnableFlashFastWakeUp()
604 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); in LL_PWR_DisableFlashFastWakeUp()
614 return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashFastWakeUp()
628 MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply); in LL_PWR_SetRegulatorSupply()
640 return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL)); in LL_PWR_GetRegulatorSupply()
652 SET_BIT(PWR->CR2, PWR_CR2_FPWM); in LL_PWR_EnableSMPSPWMMode()
662 CLEAR_BIT(PWR->CR2, PWR_CR2_FPWM); in LL_PWR_DisableSMPSPWMMode()
672 return ((READ_BIT(PWR->CR2, PWR_CR2_FPWM) == (PWR_CR2_FPWM)) ? 1UL : 0UL); in LL_PWR_IsEnabledSMPSPWMMode()
683 SET_BIT(PWR->CR3, PWR_CR3_FSTEN); in LL_PWR_EnableFastSoftStart()
693 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); in LL_PWR_DisableFastSoftStart()
703 return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledFastSoftStart()
716 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
728 return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS)); in LL_PWR_GetRegulVoltageScaling()
747 MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel); in LL_PWR_SetPVDLevel()
765 return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS)); in LL_PWR_GetPVDLevel()
775 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); in LL_PWR_EnablePVD()
785 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); in LL_PWR_DisablePVD()
795 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
814 SET_BIT(PWR->WUCR1, WakeUpPin); in LL_PWR_EnableWakeUpPin()
833 CLEAR_BIT(PWR->WUCR1, WakeUpPin); in LL_PWR_DisableWakeUpPin()
852 return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
871 SET_BIT(PWR->WUCR2, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityLow()
890 CLEAR_BIT(PWR->WUCR2, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityHigh()
909 return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL); in LL_PWR_GetWakeUpPinPolarity()
928 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal0Selection()
948 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal1Selection()
968 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal2Selection()
988 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal3Selection()
1007 return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)))); in LL_PWR_GetWakeUpPinSignalSelection()
1017 SET_BIT(PWR->DBPR, PWR_DBPR_DBP); in LL_PWR_EnableBkUpAccess()
1027 CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); in LL_PWR_DisableBkUpAccess()
1037 return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
1209 return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS)); in LL_PWR_GetRegulCurrentVOS()
1229 SET_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN); in LL_PWR_EnableREGVDDHPABypass()
1239 CLEAR_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN); in LL_PWR_DisableREGVDDHPABypass()
1249 …return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN) == (PWR_RADIOSCR_REGPABYPEN)) ? 1UL : 0U… in LL_PWR_IsEnabledREGVDDHPABypass()
1264 MODIFY_REG(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL, InputSupply); in LL_PWR_SetREGVDDHPAInputSupply()
1276 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL)); in LL_PWR_GetREGVDDHPAInputSupply()
1287 …return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA) == (PWR_RADIOSCR_REGPARDYVDDRFPA)) … in LL_PWR_IsActiveFlag_REGPARDYVDDRFPA()
1298 …return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11) == (PWR_RADIOSCR_REGPARDYV11)) ? 1UL : … in LL_PWR_IsActiveFlag_REGPARDYV11()
1309 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_RFVDDHPA)); in LL_PWR_GetRadioVDDHPAControlWord()
1319 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_ENCMODE) == (PWR_RADIOSCR_ENCMODE)) ? 1UL : 0UL); in LL_PWR_IsEnabledRadioEncryption()
1331 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_PHYMODE)); in LL_PWR_GetRadioPhyMode()
1344 if (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_1) != 0UL) in LL_PWR_GetRadioMode()
1350 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_0)); in LL_PWR_GetRadioMode()
1370 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
1381 return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1391 return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_STOP()
1403 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGULATOR()
1414 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1425 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ACTVOS()
1435 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1446 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1457 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1467 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1478 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
1489 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU6()
1499 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU7()
1509 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU8()
1520 WRITE_REG(PWR->SR, PWR_SR_CSSF); in LL_PWR_ClearFlag_STOP()
1531 WRITE_REG(PWR->SR, PWR_SR_CSSF); in LL_PWR_ClearFlag_SB()
1541 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); in LL_PWR_ClearFlag_WU1()
1552 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); in LL_PWR_ClearFlag_WU2()
1563 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); in LL_PWR_ClearFlag_WU3()
1573 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); in LL_PWR_ClearFlag_WU4()
1584 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); in LL_PWR_ClearFlag_WU5()
1595 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); in LL_PWR_ClearFlag_WU6()
1605 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); in LL_PWR_ClearFlag_WU7()
1615 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8); in LL_PWR_ClearFlag_WU8()
1625 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); in LL_PWR_ClearFlag_WU()
1644 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); in LL_PWR_EnableNSecurePrivilege()
1654 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); in LL_PWR_DisableNSecurePrivilege()
1664 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledNSecurePrivilege()
1676 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); in LL_PWR_EnableSecurePrivilege()
1686 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); in LL_PWR_DisableSecurePrivilege()
1698 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledSecurePrivilege()
1734 WRITE_REG(PWR->SECCFGR, SecureConfig); in LL_PWR_ConfigSecure()
1766 return (READ_REG(PWR->SECCFGR)); in LL_PWR_GetConfigSecure()