496   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
517   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
533   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
535   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P);  in LL_TIM_ENCODER_Init()
537   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
538   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
539   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
548   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
680   uint32_t tmpccer;  in OC1Config()  local
693   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
708   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
711   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
721     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);  in OC1Config()
724     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);  in OC1Config()
743   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
759   uint32_t tmpccer;  in OC2Config()  local
772   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
787   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
790   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
801     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);  in OC2Config()
804     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);  in OC2Config()
824   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
840   uint32_t tmpccer;  in OC3Config()  local
853   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
868   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
871   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
882     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);  in OC3Config()
885     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);  in OC3Config()
905   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
921   uint32_t tmpccer;  in OC4Config()  local
934   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
949   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
952   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
974   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
991   uint32_t tmpccer;  in OC5Config()  local
1005   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1014   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);  in OC5Config()
1017   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);  in OC5Config()
1036   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1054   uint32_t tmpccer;  in OC6Config()  local
1068   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1077   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);  in OC6Config()
1080   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);  in OC6Config()
1098   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()