Lines Matching refs:CCER
511 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
517 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
548 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
690 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
693 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
743 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
769 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
772 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
824 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
850 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
853 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
905 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
931 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); in OC4Config()
934 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
974 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1002 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); in OC5Config()
1005 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1036 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1065 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); in OC6Config()
1068 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1098 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()
1122 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; in IC1Config()
1130 MODIFY_REG(TIMx->CCER, in IC1Config()
1155 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; in IC2Config()
1164 MODIFY_REG(TIMx->CCER, in IC2Config()
1168 MODIFY_REG(TIMx->CCER, in IC2Config()
1194 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; in IC3Config()
1203 MODIFY_REG(TIMx->CCER, in IC3Config()
1207 MODIFY_REG(TIMx->CCER, in IC3Config()
1233 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; in IC4Config()
1242 MODIFY_REG(TIMx->CCER, in IC4Config()
1246 MODIFY_REG(TIMx->CCER, in IC4Config()