Lines Matching refs:htim
234 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
276 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Init() argument
279 if (htim == NULL) in HAL_TIM_Base_Init()
285 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Init()
286 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Base_Init()
287 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Base_Init()
288 assert_param(IS_TIM_PERIOD(htim->Init.Period)); in HAL_TIM_Base_Init()
289 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Base_Init()
291 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Base_Init()
294 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Base_Init()
298 TIM_ResetCallback(htim); in HAL_TIM_Base_Init()
300 if (htim->Base_MspInitCallback == NULL) in HAL_TIM_Base_Init()
302 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_Base_Init()
305 htim->Base_MspInitCallback(htim); in HAL_TIM_Base_Init()
308 HAL_TIM_Base_MspInit(htim); in HAL_TIM_Base_Init()
313 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Init()
316 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Base_Init()
320 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Base_Init()
324 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
325 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
328 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Init()
338 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_DeInit() argument
341 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_DeInit()
343 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_DeInit()
346 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_DeInit()
349 if (htim->Base_MspDeInitCallback == NULL) in HAL_TIM_Base_DeInit()
351 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_Base_DeInit()
354 htim->Base_MspDeInitCallback(htim); in HAL_TIM_Base_DeInit()
357 HAL_TIM_Base_MspDeInit(htim); in HAL_TIM_Base_DeInit()
362 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Base_DeInit()
366 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
367 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
370 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Base_DeInit()
373 __HAL_UNLOCK(htim); in HAL_TIM_Base_DeInit()
383 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspInit() argument
386 UNUSED(htim); in HAL_TIM_Base_MspInit()
398 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspDeInit() argument
401 UNUSED(htim); in HAL_TIM_Base_MspDeInit()
414 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start() argument
419 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start()
422 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start()
428 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start()
431 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start()
433 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start()
436 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
441 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
453 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop() argument
456 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop()
459 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop()
462 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop()
473 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start_IT() argument
478 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_IT()
481 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_IT()
487 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_IT()
490 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Start_IT()
493 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_IT()
495 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_IT()
498 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
503 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
515 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_IT() argument
518 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_IT()
521 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Stop_IT()
524 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_IT()
527 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_IT()
541 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L… in HAL_TIM_Base_Start_DMA() argument
546 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_DMA()
549 if (htim->State == HAL_TIM_STATE_BUSY) in HAL_TIM_Base_Start_DMA()
553 else if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_DMA()
561 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_DMA()
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_Base_Start_DMA()
571 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_Base_Start_DMA()
574 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Base_Start_DMA()
577 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->AR… in HAL_TIM_Base_Start_DMA()
585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Start_DMA()
588 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_DMA()
590 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_DMA()
593 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
598 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
610 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_DMA() argument
613 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_DMA()
616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Stop_DMA()
618 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_Base_Stop_DMA()
621 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_DMA()
624 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_DMA()
666 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_OC_Init() argument
669 if (htim == NULL) in HAL_TIM_OC_Init()
675 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_Init()
676 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OC_Init()
677 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OC_Init()
678 assert_param(IS_TIM_PERIOD(htim->Init.Period)); in HAL_TIM_OC_Init()
679 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OC_Init()
681 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OC_Init()
684 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OC_Init()
688 TIM_ResetCallback(htim); in HAL_TIM_OC_Init()
690 if (htim->OC_MspInitCallback == NULL) in HAL_TIM_OC_Init()
692 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_OC_Init()
695 htim->OC_MspInitCallback(htim); in HAL_TIM_OC_Init()
698 HAL_TIM_OC_MspInit(htim); in HAL_TIM_OC_Init()
703 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_Init()
706 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OC_Init()
710 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OC_Init()
714 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
715 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
718 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OC_Init()
728 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DeInit() argument
731 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_DeInit()
733 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_DeInit()
736 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_DeInit()
739 if (htim->OC_MspDeInitCallback == NULL) in HAL_TIM_OC_DeInit()
741 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_OC_DeInit()
744 htim->OC_MspDeInitCallback(htim); in HAL_TIM_OC_DeInit()
747 HAL_TIM_OC_MspDeInit(htim); in HAL_TIM_OC_DeInit()
752 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OC_DeInit()
756 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
757 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
760 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OC_DeInit()
763 __HAL_UNLOCK(htim); in HAL_TIM_OC_DeInit()
773 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspInit() argument
776 UNUSED(htim); in HAL_TIM_OC_MspInit()
788 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspDeInit() argument
791 UNUSED(htim); in HAL_TIM_OC_MspDeInit()
812 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start() argument
817 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Start()
820 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start()
826 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start()
829 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start()
831 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start()
834 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start()
838 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start()
840 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start()
843 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
848 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
869 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop() argument
872 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Stop()
875 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop()
877 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop()
880 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop()
884 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop()
887 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop()
904 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start_IT() argument
910 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_IT()
913 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_IT()
919 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_IT()
926 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Start_IT()
933 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Start_IT()
940 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Start_IT()
947 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Start_IT()
959 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_IT()
961 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_IT()
964 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_IT()
968 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_IT()
970 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_IT()
973 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
978 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
997 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_IT() argument
1002 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_IT()
1009 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Stop_IT()
1016 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Stop_IT()
1023 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Stop_IT()
1030 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Stop_IT()
1042 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_IT()
1044 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_IT()
1047 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1051 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1054 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_IT()
1075 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p… in HAL_TIM_OC_Start_DMA() argument
1082 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_DMA()
1085 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_OC_Start_DMA()
1089 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_DMA()
1097 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_DMA()
1110 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1111 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1114 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1117 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_OC_Start_DMA()
1125 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Start_DMA()
1132 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1133 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1136 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1139 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_OC_Start_DMA()
1147 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Start_DMA()
1154 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1155 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1158 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1161 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_OC_Start_DMA()
1168 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Start_DMA()
1175 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1176 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1179 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1182 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_OC_Start_DMA()
1189 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Start_DMA()
1201 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_DMA()
1203 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_DMA()
1206 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1210 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_DMA()
1212 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_DMA()
1215 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1220 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1239 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_DMA() argument
1244 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_DMA()
1251 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Stop_DMA()
1252 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_OC_Stop_DMA()
1259 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Stop_DMA()
1260 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_OC_Stop_DMA()
1267 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Stop_DMA()
1268 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_OC_Stop_DMA()
1275 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Stop_DMA()
1276 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_OC_Stop_DMA()
1288 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_DMA()
1290 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_DMA()
1293 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1297 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1300 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_DMA()
1343 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_Init() argument
1346 if (htim == NULL) in HAL_TIM_PWM_Init()
1352 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_Init()
1353 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_PWM_Init()
1354 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_PWM_Init()
1355 assert_param(IS_TIM_PERIOD(htim->Init.Period)); in HAL_TIM_PWM_Init()
1356 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_PWM_Init()
1358 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_PWM_Init()
1361 htim->Lock = HAL_UNLOCKED; in HAL_TIM_PWM_Init()
1365 TIM_ResetCallback(htim); in HAL_TIM_PWM_Init()
1367 if (htim->PWM_MspInitCallback == NULL) in HAL_TIM_PWM_Init()
1369 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_PWM_Init()
1372 htim->PWM_MspInitCallback(htim); in HAL_TIM_PWM_Init()
1375 HAL_TIM_PWM_MspInit(htim); in HAL_TIM_PWM_Init()
1380 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_Init()
1383 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_PWM_Init()
1387 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_PWM_Init()
1391 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1392 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1395 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_PWM_Init()
1405 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_DeInit() argument
1408 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_DeInit()
1410 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_DeInit()
1413 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_DeInit()
1416 if (htim->PWM_MspDeInitCallback == NULL) in HAL_TIM_PWM_DeInit()
1418 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_PWM_DeInit()
1421 htim->PWM_MspDeInitCallback(htim); in HAL_TIM_PWM_DeInit()
1424 HAL_TIM_PWM_MspDeInit(htim); in HAL_TIM_PWM_DeInit()
1429 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_PWM_DeInit()
1433 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1434 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1437 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_PWM_DeInit()
1440 __HAL_UNLOCK(htim); in HAL_TIM_PWM_DeInit()
1450 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspInit() argument
1453 UNUSED(htim); in HAL_TIM_PWM_MspInit()
1465 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspDeInit() argument
1468 UNUSED(htim); in HAL_TIM_PWM_MspDeInit()
1489 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start() argument
1494 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Start()
1497 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start()
1503 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start()
1506 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start()
1508 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start()
1511 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start()
1515 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start()
1517 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start()
1520 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1525 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1546 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop() argument
1549 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Stop()
1552 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop()
1554 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop()
1557 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop()
1561 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop()
1564 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop()
1581 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start_IT() argument
1587 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_IT()
1590 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_IT()
1596 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_IT()
1603 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Start_IT()
1610 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Start_IT()
1617 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Start_IT()
1624 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Start_IT()
1636 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_IT()
1638 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_IT()
1641 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1645 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_IT()
1647 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_IT()
1650 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1655 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1674 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_IT() argument
1679 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_IT()
1686 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Stop_IT()
1693 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Stop_IT()
1700 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Stop_IT()
1707 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Stop_IT()
1719 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_IT()
1721 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_IT()
1724 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1728 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1731 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_IT()
1752 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *… in HAL_TIM_PWM_Start_DMA() argument
1759 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_DMA()
1762 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_PWM_Start_DMA()
1766 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_DMA()
1774 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_DMA()
1787 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1788 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1791 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1794 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_PWM_Start_DMA()
1802 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Start_DMA()
1809 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1810 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1813 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1816 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_PWM_Start_DMA()
1823 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Start_DMA()
1830 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1831 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1834 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1837 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_PWM_Start_DMA()
1844 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Start_DMA()
1851 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1852 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1855 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1858 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_PWM_Start_DMA()
1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Start_DMA()
1877 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_DMA()
1879 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_DMA()
1882 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1886 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_DMA()
1888 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_DMA()
1891 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1896 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1915 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_DMA() argument
1920 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_DMA()
1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Stop_DMA()
1928 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_PWM_Stop_DMA()
1935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Stop_DMA()
1936 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_PWM_Stop_DMA()
1943 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Stop_DMA()
1944 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_PWM_Stop_DMA()
1951 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Stop_DMA()
1952 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_PWM_Stop_DMA()
1964 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_DMA()
1966 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_DMA()
1969 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1973 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1976 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_DMA()
2019 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_IC_Init() argument
2022 if (htim == NULL) in HAL_TIM_IC_Init()
2028 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_Init()
2029 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_IC_Init()
2030 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_IC_Init()
2031 assert_param(IS_TIM_PERIOD(htim->Init.Period)); in HAL_TIM_IC_Init()
2032 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_IC_Init()
2034 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_IC_Init()
2037 htim->Lock = HAL_UNLOCKED; in HAL_TIM_IC_Init()
2041 TIM_ResetCallback(htim); in HAL_TIM_IC_Init()
2043 if (htim->IC_MspInitCallback == NULL) in HAL_TIM_IC_Init()
2045 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_IC_Init()
2048 htim->IC_MspInitCallback(htim); in HAL_TIM_IC_Init()
2051 HAL_TIM_IC_MspInit(htim); in HAL_TIM_IC_Init()
2056 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_Init()
2059 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_IC_Init()
2063 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_IC_Init()
2067 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2068 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2071 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_IC_Init()
2081 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_DeInit() argument
2084 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_DeInit()
2086 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_DeInit()
2089 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_DeInit()
2092 if (htim->IC_MspDeInitCallback == NULL) in HAL_TIM_IC_DeInit()
2094 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_IC_DeInit()
2097 htim->IC_MspDeInitCallback(htim); in HAL_TIM_IC_DeInit()
2100 HAL_TIM_IC_MspDeInit(htim); in HAL_TIM_IC_DeInit()
2105 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_IC_DeInit()
2109 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2110 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2113 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_IC_DeInit()
2116 __HAL_UNLOCK(htim); in HAL_TIM_IC_DeInit()
2126 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspInit() argument
2129 UNUSED(htim); in HAL_TIM_IC_MspInit()
2141 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspDeInit() argument
2144 UNUSED(htim); in HAL_TIM_IC_MspDeInit()
2162 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start() argument
2165 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2166 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2169 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start()
2179 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2180 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2183 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start()
2186 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start()
2188 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start()
2191 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2196 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2214 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop() argument
2217 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop()
2220 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop()
2223 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop()
2226 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2227 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2244 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start_IT() argument
2249 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2250 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2253 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_IT()
2263 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2264 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2271 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Start_IT()
2278 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Start_IT()
2285 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Start_IT()
2292 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Start_IT()
2304 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_IT()
2307 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_IT()
2309 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_IT()
2312 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2317 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2336 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_IT() argument
2341 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_IT()
2348 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Stop_IT()
2355 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Stop_IT()
2362 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Stop_IT()
2369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Stop_IT()
2381 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_IT()
2384 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_IT()
2387 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2388 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2409 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, … in HAL_TIM_IC_Start_DMA() argument
2414 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2415 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2418 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_DMA()
2419 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Start_DMA()
2436 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2437 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2446 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_DMA()
2453 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2454 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2457 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2460 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2467 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Start_DMA()
2474 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2475 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2478 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2481 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2488 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Start_DMA()
2495 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2496 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2499 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2502 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2509 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Start_DMA()
2516 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2517 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2520 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2523 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2530 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Start_DMA()
2540 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_DMA()
2542 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_DMA()
2545 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2550 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2568 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_DMA() argument
2573 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_DMA()
2574 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Stop_DMA()
2577 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_DMA()
2584 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Stop_DMA()
2585 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_IC_Stop_DMA()
2592 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Stop_DMA()
2593 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_IC_Stop_DMA()
2600 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Stop_DMA()
2601 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_IC_Stop_DMA()
2608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Stop_DMA()
2609 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_IC_Stop_DMA()
2621 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_DMA()
2624 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2625 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2674 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) in HAL_TIM_OnePulse_Init() argument
2677 if (htim == NULL) in HAL_TIM_OnePulse_Init()
2683 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_Init()
2684 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OnePulse_Init()
2685 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OnePulse_Init()
2687 assert_param(IS_TIM_PERIOD(htim->Init.Period)); in HAL_TIM_OnePulse_Init()
2688 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OnePulse_Init()
2690 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OnePulse_Init()
2693 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OnePulse_Init()
2697 TIM_ResetCallback(htim); in HAL_TIM_OnePulse_Init()
2699 if (htim->OnePulse_MspInitCallback == NULL) in HAL_TIM_OnePulse_Init()
2701 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_OnePulse_Init()
2704 htim->OnePulse_MspInitCallback(htim); in HAL_TIM_OnePulse_Init()
2707 HAL_TIM_OnePulse_MspInit(htim); in HAL_TIM_OnePulse_Init()
2712 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_Init()
2715 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OnePulse_Init()
2718 htim->Instance->CR1 &= ~TIM_CR1_OPM; in HAL_TIM_OnePulse_Init()
2721 htim->Instance->CR1 |= OnePulseMode; in HAL_TIM_OnePulse_Init()
2725 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OnePulse_Init()
2729 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2730 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2731 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2732 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2735 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_Init()
2745 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_DeInit() argument
2748 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_DeInit()
2750 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_DeInit()
2753 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_DeInit()
2756 if (htim->OnePulse_MspDeInitCallback == NULL) in HAL_TIM_OnePulse_DeInit()
2758 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_OnePulse_DeInit()
2761 htim->OnePulse_MspDeInitCallback(htim); in HAL_TIM_OnePulse_DeInit()
2764 HAL_TIM_OnePulse_MspDeInit(htim); in HAL_TIM_OnePulse_DeInit()
2769 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2773 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2774 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2775 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2776 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2779 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2782 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_DeInit()
2792 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspInit() argument
2795 UNUSED(htim); in HAL_TIM_OnePulse_MspInit()
2807 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspDeInit() argument
2810 UNUSED(htim); in HAL_TIM_OnePulse_MspDeInit()
2827 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start() argument
2829 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start()
2830 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start()
2831 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2832 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2847 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2848 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2849 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2850 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2861 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2862 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2864 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start()
2867 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start()
2884 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop() argument
2895 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2896 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2898 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop()
2901 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2905 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2908 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2909 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2910 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2911 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2927 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start_IT() argument
2929 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start_IT()
2930 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start_IT()
2931 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2932 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2947 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2948 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2949 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2950 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2962 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Start_IT()
2965 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Start_IT()
2967 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2968 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2970 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start_IT()
2973 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start_IT()
2990 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop_IT() argument
2996 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Stop_IT()
2999 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Stop_IT()
3006 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
3007 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
3009 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop_IT()
3012 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
3016 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
3019 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
3020 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
3021 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
3022 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
3069 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon… in HAL_TIM_Encoder_Init() argument
3076 if (htim == NULL) in HAL_TIM_Encoder_Init()
3082 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Init()
3083 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Encoder_Init()
3084 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Encoder_Init()
3085 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Encoder_Init()
3095 assert_param(IS_TIM_PERIOD(htim->Init.Period)); in HAL_TIM_Encoder_Init()
3097 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Encoder_Init()
3100 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Encoder_Init()
3104 TIM_ResetCallback(htim); in HAL_TIM_Encoder_Init()
3106 if (htim->Encoder_MspInitCallback == NULL) in HAL_TIM_Encoder_Init()
3108 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_Encoder_Init()
3111 htim->Encoder_MspInitCallback(htim); in HAL_TIM_Encoder_Init()
3114 HAL_TIM_Encoder_MspInit(htim); in HAL_TIM_Encoder_Init()
3119 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_Init()
3122 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); in HAL_TIM_Encoder_Init()
3125 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Encoder_Init()
3128 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_Encoder_Init()
3131 tmpccmr1 = htim->Instance->CCMR1; in HAL_TIM_Encoder_Init()
3134 tmpccer = htim->Instance->CCER; in HAL_TIM_Encoder_Init()
3158 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_Encoder_Init()
3161 htim->Instance->CCMR1 = tmpccmr1; in HAL_TIM_Encoder_Init()
3164 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
3168 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Encoder_Init()
3172 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3173 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3174 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3175 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3178 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Encoder_Init()
3189 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_DeInit() argument
3192 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_DeInit()
3194 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_DeInit()
3197 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_DeInit()
3200 if (htim->Encoder_MspDeInitCallback == NULL) in HAL_TIM_Encoder_DeInit()
3202 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_Encoder_DeInit()
3205 htim->Encoder_MspDeInitCallback(htim); in HAL_TIM_Encoder_DeInit()
3208 HAL_TIM_Encoder_MspDeInit(htim); in HAL_TIM_Encoder_DeInit()
3213 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3217 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3218 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3219 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3220 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3223 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3226 __HAL_UNLOCK(htim); in HAL_TIM_Encoder_DeInit()
3236 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspInit() argument
3239 UNUSED(htim); in HAL_TIM_Encoder_MspInit()
3251 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspDeInit() argument
3254 UNUSED(htim); in HAL_TIM_Encoder_MspDeInit()
3271 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start() argument
3273 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start()
3274 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start()
3275 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3276 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3279 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start()
3291 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3292 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3304 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3305 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3319 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3320 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3321 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3322 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3331 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3337 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3343 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3349 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start()
3365 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop() argument
3368 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop()
3376 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3382 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3388 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3389 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3395 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop()
3400 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3401 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3405 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3406 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3407 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3408 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3425 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start_IT() argument
3427 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_IT()
3428 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_IT()
3429 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3430 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3433 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_IT()
3445 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3446 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3458 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3459 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3473 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3474 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3475 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3476 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3487 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3493 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3494 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3500 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3501 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3502 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3503 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3509 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_IT()
3525 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_IT() argument
3528 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_IT()
3534 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3537 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3541 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3544 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3548 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3549 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3552 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3553 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3557 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_IT()
3562 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3563 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3567 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3568 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3569 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3570 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3591 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD… in HAL_TIM_Encoder_Start_DMA() argument
3594 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_DMA()
3595 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_DMA()
3596 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3597 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3600 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_DMA()
3619 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3620 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3644 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3645 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3673 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3674 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3675 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3676 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3690 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3691 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3694 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3697 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3704 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3707 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3710 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3718 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3719 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3722 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; in HAL_TIM_Encoder_Start_DMA()
3724 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3731 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3734 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3737 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3745 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3746 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3749 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3752 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3760 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3761 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3764 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3767 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3775 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3777 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3780 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3781 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3784 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3804 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_DMA() argument
3807 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_DMA()
3813 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3816 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3817 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3821 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3824 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3825 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3829 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3833 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3834 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3835 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3836 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3840 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_DMA()
3845 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3846 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3850 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3851 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3852 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3853 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3882 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) in HAL_TIM_IRQHandler() argument
3884 uint32_t itsource = htim->Instance->DIER; in HAL_TIM_IRQHandler()
3885 uint32_t itflag = htim->Instance->SR; in HAL_TIM_IRQHandler()
3893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); in HAL_TIM_IRQHandler()
3894 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in HAL_TIM_IRQHandler()
3897 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) in HAL_TIM_IRQHandler()
3900 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3902 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3909 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3910 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3912 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3913 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3916 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3925 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); in HAL_TIM_IRQHandler()
3926 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in HAL_TIM_IRQHandler()
3928 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) in HAL_TIM_IRQHandler()
3931 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3933 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3940 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3941 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3943 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3944 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3947 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3955 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); in HAL_TIM_IRQHandler()
3956 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in HAL_TIM_IRQHandler()
3958 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) in HAL_TIM_IRQHandler()
3961 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3963 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3970 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3971 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3973 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3974 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3977 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3985 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); in HAL_TIM_IRQHandler()
3986 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in HAL_TIM_IRQHandler()
3988 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) in HAL_TIM_IRQHandler()
3991 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3993 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
4000 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
4001 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
4003 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
4004 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
4007 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
4015 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); in HAL_TIM_IRQHandler()
4017 htim->PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
4019 HAL_TIM_PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
4028 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); in HAL_TIM_IRQHandler()
4030 htim->BreakCallback(htim); in HAL_TIM_IRQHandler()
4032 HAL_TIMEx_BreakCallback(htim); in HAL_TIM_IRQHandler()
4042 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); in HAL_TIM_IRQHandler()
4044 htim->Break2Callback(htim); in HAL_TIM_IRQHandler()
4046 HAL_TIMEx_Break2Callback(htim); in HAL_TIM_IRQHandler()
4056 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_IRQHandler()
4058 htim->TriggerCallback(htim); in HAL_TIM_IRQHandler()
4060 HAL_TIM_TriggerCallback(htim); in HAL_TIM_IRQHandler()
4069 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); in HAL_TIM_IRQHandler()
4071 htim->CommutationCallback(htim); in HAL_TIM_IRQHandler()
4073 HAL_TIMEx_CommutCallback(htim); in HAL_TIM_IRQHandler()
4118 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_OC_ConfigChannel() argument
4130 __HAL_LOCK(htim); in HAL_TIM_OC_ConfigChannel()
4137 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4140 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4147 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4150 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4157 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4160 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4167 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4170 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4178 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4181 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4190 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4193 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4203 __HAL_UNLOCK(htim); in HAL_TIM_OC_ConfigChannel()
4221 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf… in HAL_TIM_IC_ConfigChannel() argument
4226 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4233 __HAL_LOCK(htim); in HAL_TIM_IC_ConfigChannel()
4238 TIM_TI1_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4244 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_IC_ConfigChannel()
4247 htim->Instance->CCMR1 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4252 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4254 TIM_TI2_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4260 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_IC_ConfigChannel()
4263 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4268 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4270 TIM_TI3_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4276 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; in HAL_TIM_IC_ConfigChannel()
4279 htim->Instance->CCMR2 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4284 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4286 TIM_TI4_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4292 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; in HAL_TIM_IC_ConfigChannel()
4295 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4302 __HAL_UNLOCK(htim); in HAL_TIM_IC_ConfigChannel()
4323 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_PWM_ConfigChannel() argument
4336 __HAL_LOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4343 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4346 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4349 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; in HAL_TIM_PWM_ConfigChannel()
4352 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; in HAL_TIM_PWM_ConfigChannel()
4353 htim->Instance->CCMR1 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4360 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4363 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4366 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; in HAL_TIM_PWM_ConfigChannel()
4369 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; in HAL_TIM_PWM_ConfigChannel()
4370 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4377 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4380 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4383 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; in HAL_TIM_PWM_ConfigChannel()
4386 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; in HAL_TIM_PWM_ConfigChannel()
4387 htim->Instance->CCMR2 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4394 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4397 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4400 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; in HAL_TIM_PWM_ConfigChannel()
4403 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; in HAL_TIM_PWM_ConfigChannel()
4404 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4412 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4415 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4418 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; in HAL_TIM_PWM_ConfigChannel()
4421 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; in HAL_TIM_PWM_ConfigChannel()
4422 htim->Instance->CCMR3 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4431 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4434 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4437 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; in HAL_TIM_PWM_ConfigChannel()
4440 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; in HAL_TIM_PWM_ConfigChannel()
4441 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4451 __HAL_UNLOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4475 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef… in HAL_TIM_OnePulse_ConfigChannel() argument
4488 __HAL_LOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4490 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_ConfigChannel()
4504 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4506 TIM_OC1_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4512 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4514 TIM_OC2_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4529 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4531 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4535 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_OnePulse_ConfigChannel()
4538 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4539 htim->Instance->SMCR |= TIM_TS_TI1FP1; in HAL_TIM_OnePulse_ConfigChannel()
4542 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4543 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4549 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4551 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4555 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_OnePulse_ConfigChannel()
4558 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4559 htim->Instance->SMCR |= TIM_TS_TI2FP2; in HAL_TIM_OnePulse_ConfigChannel()
4562 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4563 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4573 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_ConfigChannel()
4575 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4624 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_WriteStart() argument
4629 …status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu… in HAL_TIM_DMABurst_WriteStart()
4676 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre… in HAL_TIM_DMABurst_MultiWriteStart() argument
4683 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiWriteStart()
4689 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiWriteStart()
4693 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiWriteStart()
4701 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiWriteStart()
4714 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4715 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4718 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4721 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4722 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4732 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4733 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4736 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4739 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4740 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4750 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4751 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4754 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4757 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4758 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4768 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4769 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4772 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4775 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4776 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4786 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4787 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4790 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4793 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4794 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4809 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiWriteStart()
4811 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiWriteStart()
4824 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_WriteStop() argument
4836 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_WriteStop()
4841 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_WriteStop()
4846 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_WriteStop()
4851 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_WriteStop()
4856 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_WriteStop()
4867 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_WriteStop()
4870 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_WriteStop()
4915 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_ReadStart() argument
4920 …status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bur… in HAL_TIM_DMABurst_ReadStart()
4966 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres… in HAL_TIM_DMABurst_MultiReadStart() argument
4973 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiReadStart()
4979 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiReadStart()
4983 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiReadStart()
4991 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiReadStart()
5003 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiReadStart()
5004 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5007 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5010 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bur… in HAL_TIM_DMABurst_MultiReadStart()
5021 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5022 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5025 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5028 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5039 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5040 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5043 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5046 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5057 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5058 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5061 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5064 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5075 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5076 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5079 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5082 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5098 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiReadStart()
5101 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiReadStart()
5114 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_ReadStop() argument
5126 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_ReadStop()
5131 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_ReadStop()
5136 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_ReadStop()
5141 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_ReadStop()
5146 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_ReadStop()
5157 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_ReadStop()
5160 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_ReadStop()
5189 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) in HAL_TIM_GenerateEvent() argument
5192 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_GenerateEvent()
5196 __HAL_LOCK(htim); in HAL_TIM_GenerateEvent()
5199 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_GenerateEvent()
5202 htim->Instance->EGR = EventSource; in HAL_TIM_GenerateEvent()
5205 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_GenerateEvent()
5207 __HAL_UNLOCK(htim); in HAL_TIM_GenerateEvent()
5229 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, in HAL_TIM_ConfigOCrefClear() argument
5236 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigOCrefClear()
5240 __HAL_LOCK(htim); in HAL_TIM_ConfigOCrefClear()
5242 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigOCrefClear()
5249 …CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM… in HAL_TIM_ConfigOCrefClear()
5263 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5264 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5268 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigOCrefClear()
5274 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); in HAL_TIM_ConfigOCrefClear()
5292 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5297 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5306 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5311 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5320 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5325 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5334 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5339 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5349 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5354 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5365 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5370 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5380 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5382 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5394 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *… in HAL_TIM_ConfigClockSource() argument
5400 __HAL_LOCK(htim); in HAL_TIM_ConfigClockSource()
5402 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigClockSource()
5408 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5411 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5417 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5424 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5432 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5438 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5441 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5448 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5456 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5461 htim->Instance->SMCR |= TIM_SMCR_ECE; in HAL_TIM_ConfigClockSource()
5468 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5474 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5477 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); in HAL_TIM_ConfigClockSource()
5484 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5490 TIM_TI2_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5493 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); in HAL_TIM_ConfigClockSource()
5500 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5506 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5509 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); in HAL_TIM_ConfigClockSource()
5518 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigClockSource()
5520 __HAL_UNLOCK(htim); in HAL_TIM_ConfigClockSource()
5537 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) in HAL_TIM_ConfigTI1Input() argument
5542 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigTI1Input()
5546 tmpcr2 = htim->Instance->CR2; in HAL_TIM_ConfigTI1Input()
5555 htim->Instance->CR2 = tmpcr2; in HAL_TIM_ConfigTI1Input()
5569 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef … in HAL_TIM_SlaveConfigSynchro() argument
5572 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro()
5576 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5578 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro()
5580 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro()
5582 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5583 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5588 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro()
5591 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5593 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5607 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, in HAL_TIM_SlaveConfigSynchro_IT() argument
5611 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro_IT()
5615 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5617 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro_IT()
5619 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro_IT()
5621 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5622 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5627 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro_IT()
5630 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5632 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5648 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_ReadCapturedValue() argument
5657 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5660 tmpreg = htim->Instance->CCR1; in HAL_TIM_ReadCapturedValue()
5667 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5670 tmpreg = htim->Instance->CCR2; in HAL_TIM_ReadCapturedValue()
5678 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5681 tmpreg = htim->Instance->CCR3; in HAL_TIM_ReadCapturedValue()
5689 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5692 tmpreg = htim->Instance->CCR4; in HAL_TIM_ReadCapturedValue()
5732 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedCallback() argument
5735 UNUSED(htim); in HAL_TIM_PeriodElapsedCallback()
5748 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedHalfCpltCallback() argument
5751 UNUSED(htim); in HAL_TIM_PeriodElapsedHalfCpltCallback()
5764 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DelayElapsedCallback() argument
5767 UNUSED(htim); in HAL_TIM_OC_DelayElapsedCallback()
5779 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureCallback() argument
5782 UNUSED(htim); in HAL_TIM_IC_CaptureCallback()
5795 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureHalfCpltCallback() argument
5798 UNUSED(htim); in HAL_TIM_IC_CaptureHalfCpltCallback()
5811 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedCallback() argument
5814 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedCallback()
5827 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedHalfCpltCallback() argument
5830 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
5843 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) in HAL_TIM_TriggerCallback() argument
5846 UNUSED(htim); in HAL_TIM_TriggerCallback()
5859 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) in HAL_TIM_ErrorCallback() argument
5862 UNUSED(htim); in HAL_TIM_ErrorCallback()
5905 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb… in HAL_TIM_RegisterCallback() argument
5915 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_RegisterCallback()
5920 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5924 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5928 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5932 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5936 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5940 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5944 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5948 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5952 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5956 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5960 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5964 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
5968 htim->PeriodElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
5973 htim->PeriodElapsedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
5978 htim->TriggerCallback = pCallback; in HAL_TIM_RegisterCallback()
5982 htim->IC_CaptureCallback = pCallback; in HAL_TIM_RegisterCallback()
5987 htim->IC_CaptureHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
5992 htim->OC_DelayElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
5996 htim->PWM_PulseFinishedCallback = pCallback; in HAL_TIM_RegisterCallback()
6001 htim->PWM_PulseFinishedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6005 htim->ErrorCallback = pCallback; in HAL_TIM_RegisterCallback()
6010 htim->CommutationCallback = pCallback; in HAL_TIM_RegisterCallback()
6014 htim->BreakCallback = pCallback; in HAL_TIM_RegisterCallback()
6019 htim->Break2Callback = pCallback; in HAL_TIM_RegisterCallback()
6029 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_RegisterCallback()
6034 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6038 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6042 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6046 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6050 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6054 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6058 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6062 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6066 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6070 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6074 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6078 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6130 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal… in HAL_TIM_UnRegisterCallback() argument
6134 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_UnRegisterCallback()
6140 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6145 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6150 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6155 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6160 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6165 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6170 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6175 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6180 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6185 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6190 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6195 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6200 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in HAL_TIM_UnRegisterCallback()
6206 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6212 htim->TriggerCallback = HAL_TIM_TriggerCallback; in HAL_TIM_UnRegisterCallback()
6217 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in HAL_TIM_UnRegisterCallback()
6223 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6229 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in HAL_TIM_UnRegisterCallback()
6234 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in HAL_TIM_UnRegisterCallback()
6240 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6245 htim->ErrorCallback = HAL_TIM_ErrorCallback; in HAL_TIM_UnRegisterCallback()
6251 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in HAL_TIM_UnRegisterCallback()
6256 htim->BreakCallback = HAL_TIMEx_BreakCallback; in HAL_TIM_UnRegisterCallback()
6262 htim->Break2Callback = HAL_TIMEx_Break2Callback; in HAL_TIM_UnRegisterCallback()
6272 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_UnRegisterCallback()
6278 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6283 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6288 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6293 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6298 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6303 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6308 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6313 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6318 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6323 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6328 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6333 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6376 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Base_GetState() argument
6378 return htim->State; in HAL_TIM_Base_GetState()
6386 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OC_GetState() argument
6388 return htim->State; in HAL_TIM_OC_GetState()
6396 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_PWM_GetState() argument
6398 return htim->State; in HAL_TIM_PWM_GetState()
6406 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_IC_GetState() argument
6408 return htim->State; in HAL_TIM_IC_GetState()
6416 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_GetState() argument
6418 return htim->State; in HAL_TIM_OnePulse_GetState()
6426 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_GetState() argument
6428 return htim->State; in HAL_TIM_Encoder_GetState()
6436 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) in HAL_TIM_GetActiveChannel() argument
6438 return htim->Channel; in HAL_TIM_GetActiveChannel()
6454 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channe… in HAL_TIM_GetChannelState() argument
6459 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_GetChannelState()
6461 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_GetChannelState()
6472 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) in HAL_TIM_DMABurstState() argument
6475 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurstState()
6477 return htim->DMABurstState; in HAL_TIM_DMABurstState()
6501 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAError() local
6503 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMAError()
6505 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMAError()
6506 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6508 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMAError()
6510 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMAError()
6511 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6513 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMAError()
6515 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMAError()
6516 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6518 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMAError()
6520 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMAError()
6521 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6525 htim->State = HAL_TIM_STATE_READY; in TIM_DMAError()
6529 htim->ErrorCallback(htim); in TIM_DMAError()
6531 HAL_TIM_ErrorCallback(htim); in TIM_DMAError()
6534 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMAError()
6544 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseCplt() local
6546 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseCplt()
6548 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseCplt()
6552 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6555 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseCplt()
6557 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseCplt()
6561 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6564 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseCplt()
6566 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseCplt()
6570 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6573 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseCplt()
6575 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseCplt()
6579 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6588 htim->PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6590 HAL_TIM_PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6593 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseCplt()
6603 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseHalfCplt() local
6605 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseHalfCplt()
6607 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseHalfCplt()
6609 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseHalfCplt()
6611 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseHalfCplt()
6613 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseHalfCplt()
6615 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseHalfCplt()
6617 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseHalfCplt()
6619 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseHalfCplt()
6627 htim->PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6629 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6632 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseHalfCplt()
6642 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureCplt() local
6644 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureCplt()
6646 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureCplt()
6650 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6651 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6654 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureCplt()
6656 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureCplt()
6660 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6661 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6664 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureCplt()
6666 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureCplt()
6670 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6671 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6674 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureCplt()
6676 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureCplt()
6680 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6681 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6690 htim->IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6692 HAL_TIM_IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6695 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureCplt()
6705 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureHalfCplt() local
6707 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureHalfCplt()
6709 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureHalfCplt()
6711 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureHalfCplt()
6713 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureHalfCplt()
6715 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureHalfCplt()
6717 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureHalfCplt()
6719 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureHalfCplt()
6721 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureHalfCplt()
6729 htim->IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
6731 HAL_TIM_IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
6734 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureHalfCplt()
6744 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedCplt() local
6746 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) in TIM_DMAPeriodElapsedCplt()
6748 htim->State = HAL_TIM_STATE_READY; in TIM_DMAPeriodElapsedCplt()
6752 htim->PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
6754 HAL_TIM_PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
6765 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedHalfCplt() local
6768 htim->PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
6770 HAL_TIM_PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
7240 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, in TIM_SlaveTimer_SetConfig() argument
7249 tmpsmcr = htim->Instance->SMCR; in TIM_SlaveTimer_SetConfig()
7262 htim->Instance->SMCR = tmpsmcr; in TIM_SlaveTimer_SetConfig()
7270 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7275 TIM_ETR_SetConfig(htim->Instance, in TIM_SlaveTimer_SetConfig()
7285 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7294 tmpccer = htim->Instance->CCER; in TIM_SlaveTimer_SetConfig()
7295 htim->Instance->CCER &= ~TIM_CCER_CC1E; in TIM_SlaveTimer_SetConfig()
7296 tmpccmr1 = htim->Instance->CCMR1; in TIM_SlaveTimer_SetConfig()
7303 htim->Instance->CCMR1 = tmpccmr1; in TIM_SlaveTimer_SetConfig()
7304 htim->Instance->CCER = tmpccer; in TIM_SlaveTimer_SetConfig()
7311 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7316 TIM_TI1_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7325 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7330 TIM_TI2_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7715 void TIM_ResetCallback(TIM_HandleTypeDef *htim) in TIM_ResetCallback() argument
7718 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in TIM_ResetCallback()
7720 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in TIM_ResetCallback()
7722 htim->TriggerCallback = HAL_TIM_TriggerCallback; in TIM_ResetCallback()
7723 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in TIM_ResetCallback()
7725 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in TIM_ResetCallback()
7727 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in TIM_ResetCallback()
7728 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in TIM_ResetCallback()
7730 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in TIM_ResetCallback()
7731 htim->ErrorCallback = HAL_TIM_ErrorCallback; in TIM_ResetCallback()
7733 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in TIM_ResetCallback()
7734 htim->BreakCallback = HAL_TIMEx_BreakCallback; in TIM_ResetCallback()
7736 htim->Break2Callback = HAL_TIMEx_Break2Callback; in TIM_ResetCallback()