Lines Matching refs:PWR
34 #if defined(PWR)
176 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
177 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
421 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
428 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
454 SET_BIT(PWR->CR1, PWR_CR1_ENSDNBOR); in LL_PWR_EnableBORinSDN()
464 CLEAR_BIT(PWR->CR1, PWR_CR1_ENSDNBOR); in LL_PWR_DisableBORinSDN()
474 return ((READ_BIT(PWR->CR1, PWR_CR1_ENSDNBOR) == (PWR_CR1_ENSDNBOR)) ? 1UL : 0UL); in LL_PWR_IsEnabledBORinSDN()
487 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); in LL_PWR_SetPowerMode()
500 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
510 SET_BIT(PWR->CR1, PWR_CR1_APC); in LL_PWR_EnablePUPDCfg()
520 CLEAR_BIT(PWR->CR1, PWR_CR1_APC); in LL_PWR_DisablePUPDCfg()
530 return ((READ_BIT(PWR->CR1, PWR_CR1_APC) == (PWR_CR1_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDCfg()
542 SET_BIT(PWR->CR2, PWR_CR2_LSILPMUFEN); in LL_PWR_EnableLSILPMU()
553 CLEAR_BIT(PWR->CR2, PWR_CR2_LSILPMUFEN); in LL_PWR_DisableLSILPMU()
563 return ((READ_BIT(PWR->CR2, PWR_CR2_LSILPMUFEN) == (PWR_CR2_LSILPMUFEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledLSILPMU()
575 SET_BIT(PWR->CR2, PWR_CR2_ENTS); in LL_PWR_EnableTempSens()
585 CLEAR_BIT(PWR->CR2, PWR_CR2_ENTS); in LL_PWR_DisableTempSens()
595 return ((READ_BIT(PWR->CR2, PWR_CR2_ENTS) == (PWR_CR2_ENTS)) ? 1UL : 0UL); in LL_PWR_IsEnabledTempSens()
613 SET_BIT(PWR->CR2, banks); in LL_PWR_EnableRAMBankRet()
631 ram_ret = READ_BIT(PWR->CR2, (PWR_CR2_RAMRET1)); in LL_PWR_GetRAMBankRet()
633 ram_ret |= READ_BIT(PWR->CR2, (PWR_CR2_RAMRET2)); in LL_PWR_GetRAMBankRet()
636 ram_ret |= READ_BIT(PWR->CR2, (PWR_CR2_RAMRET3)); in LL_PWR_GetRAMBankRet()
655 CLEAR_BIT(PWR->CR2, banks); in LL_PWR_DisableRAMBankRet()
674 MODIFY_REG(PWR->CR2, PWR_CR2_PVDLS, PVDLevel); in LL_PWR_SetPVDLevel()
692 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDLS)); in LL_PWR_GetPVDLevel()
702 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
712 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
722 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
739 SET_BIT(PWR->CR2, PWR_CR2_GPIORET); in LL_PWR_EnableGPIORET()
749 CLEAR_BIT(PWR->CR2, PWR_CR2_GPIORET); in LL_PWR_DisableGPIORET()
759 return ((READ_BIT(PWR->CR2, PWR_CR2_GPIORET) == (PWR_CR2_GPIORET)) ? 1UL : 0UL); in LL_PWR_IsEnabledGPIORET()
780 SET_BIT(PWR->CR2, PWR_CR2_DBGRET); in LL_PWR_EnableDBGRET()
791 CLEAR_BIT(PWR->CR2, PWR_CR2_DBGRET); in LL_PWR_DisableDBGRET()
802 return ((READ_BIT(PWR->CR2, PWR_CR2_DBGRET) == (PWR_CR2_DBGRET)) ? 1UL : 0UL); in LL_PWR_IsEnabledDBGRET()
816 SET_BIT(PWR->CR3, PWR_CR3_EIWL); in LL_PWR_EnableInternWU()
826 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWL); in LL_PWR_DisableInternWU()
836 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWL) == (PWR_CR3_EIWL)) ? 1UL : 0UL); in LL_PWR_IsEnabledInternWU()
847 SET_BIT(PWR->CR3, PWR_CR3_EIWL2); in LL_PWR_EnableInternWU2()
857 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWL2); in LL_PWR_DisableInternWU2()
867 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWL2) == (PWR_CR3_EIWL2)) ? 1UL : 0UL); in LL_PWR_IsEnabledInternWU2()
877 WRITE_REG(PWR->SR1, PWR_SR1_IWUF2); in LL_PWR_ClearFlag_InternWU2()
952 SET_BIT(PWR->CR3, (WakeUpPin & 0x0000FFFF)); in LL_PWR_EnableWakeUpPin()
953 SET_BIT(PWR->CR6, (WakeUpPin >> 16)); in LL_PWR_EnableWakeUpPin()
1026 CLEAR_BIT(PWR->CR3, (WakeUpPin & 0x0000FFFF)); in LL_PWR_DisableWakeUpPin()
1027 CLEAR_BIT(PWR->CR6, (WakeUpPin >> 16)); in LL_PWR_DisableWakeUpPin()
1099 return ((READ_BIT(PWR->CR3, (WakeUpPin & 0x0000FFFF)) == (WakeUpPin & 0x0000FFFF)) && in LL_PWR_IsEnabledWakeUpPin()
1100 (READ_BIT(PWR->CR6, (WakeUpPin >> 16)) == (WakeUpPin >> 16)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
1164 SET_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF)); in LL_PWR_SetWakeUpPinPolarityLow()
1165 SET_BIT(PWR->CR7, (WakeUpPin >> 16)); in LL_PWR_SetWakeUpPinPolarityLow()
1230 CLEAR_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF)); in LL_PWR_SetWakeUpPinPolarityHigh()
1231 CLEAR_BIT(PWR->CR7, (WakeUpPin >> 16)); in LL_PWR_SetWakeUpPinPolarityHigh()
1299 return (uint32_t)((READ_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF))) ? 1UL : 0UL); in LL_PWR_IsWakeUpPinPolarityLow()
1303 return (uint32_t)((READ_BIT(PWR->CR7, (WakeUpPin >> 16))) ? 1UL : 0UL); in LL_PWR_IsWakeUpPinPolarityLow()
1315 SET_BIT(PWR->CR3, PWR_CR3_EWBLE); in LL_PWR_EnableWU_EWBLE()
1325 SET_BIT(PWR->CR3, PWR_CR3_EWBLEHCPU); in LL_PWR_EnableWU_EWBLEHCPU()
1335 CLEAR_BIT(PWR->CR3, PWR_CR3_EWBLE); in LL_PWR_DisableWU_EWBLE()
1345 CLEAR_BIT(PWR->CR3, PWR_CR3_EWBLEHCPU); in LL_PWR_DisableWU_EWBLEHCPU()
1355 return ((READ_BIT(PWR->CR3, PWR_CR3_EWBLE) == (PWR_CR3_EWBLE)) ? 1UL : 0UL); in LL_PWR_IsEnabledWU_EWBLE()
1365 return ((READ_BIT(PWR->CR3, PWR_CR3_EWBLEHCPU) == (PWR_CR3_EWBLEHCPU)) ? 1UL : 0UL); in LL_PWR_IsEnabledWU_EWBLEHCPU()
1383 return ((READ_BIT(PWR->SR1, PWR_SR1_IWUF) == (PWR_SR1_IWUF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_InternWU()
1394 return ((READ_BIT(PWR->SR1, PWR_SR1_IWUF2) == (PWR_SR1_IWUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_InternWU2()
1405 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF0) == (PWR_SR1_WUF0)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU0()
1415 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1425 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1434 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1444 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1454 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
1464 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU6()
1474 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF7) == (PWR_SR1_WUF7)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU7()
1484 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF8) == (PWR_SR1_WUF8)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU8()
1494 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF9) == (PWR_SR1_WUF9)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU9()
1504 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF10) == (PWR_SR1_WUF10)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU10()
1514 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF11) == (PWR_SR1_WUF11)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU11()
1524 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF12) == (PWR_SR3_WUF12)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU12()
1534 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF13) == (PWR_SR3_WUF13)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU13()
1544 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF14) == (PWR_SR3_WUF14)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU14()
1554 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF15) == (PWR_SR3_WUF15)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU15()
1564 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF16) == (PWR_SR3_WUF16)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU16()
1574 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF17) == (PWR_SR3_WUF17)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU17()
1584 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF18) == (PWR_SR3_WUF18)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU18()
1594 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF19) == (PWR_SR3_WUF19)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU19()
1605 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF20) == (PWR_SR3_WUF20)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU20()
1617 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF21) == (PWR_SR3_WUF21)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU21()
1629 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF22) == (PWR_SR3_WUF22)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU22()
1641 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF23) == (PWR_SR3_WUF23)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU23()
1653 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF24) == (PWR_SR3_WUF24)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU24()
1665 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF25) == (PWR_SR3_WUF25)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU25()
1677 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF26) == (PWR_SR3_WUF26)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU26()
1689 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF27) == (PWR_SR3_WUF27)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU27()
1767 wakeup_source = READ_REG(PWR->SR1) & 0x0000FFFF; in LL_PWR_GetWakeupSource()
1768 return (uint32_t)(wakeup_source | (READ_REG(PWR->SR3) << 16)); in LL_PWR_GetWakeupSource()
1842 WRITE_REG(PWR->SR1, (source & 0x0000FFFF)); in LL_PWR_ClearWakeupSource()
1843 WRITE_REG(PWR->SR3, (source >> 16)); in LL_PWR_ClearWakeupSource()
1853 WRITE_REG(PWR->SR1, PWR_SR1_WUF0); in LL_PWR_ClearFlag_WU0()
1863 WRITE_REG(PWR->SR1, PWR_SR1_WUF1); in LL_PWR_ClearFlag_WU1()
1874 WRITE_REG(PWR->SR1, PWR_SR1_WUF2); in LL_PWR_ClearFlag_WU2()
1884 WRITE_REG(PWR->SR1, PWR_SR1_WUF3); in LL_PWR_ClearFlag_WU3()
1894 WRITE_REG(PWR->SR1, PWR_SR1_WUF4); in LL_PWR_ClearFlag_WU4()
1904 WRITE_REG(PWR->SR1, PWR_SR1_WUF5); in LL_PWR_ClearFlag_WU5()
1914 WRITE_REG(PWR->SR1, PWR_SR1_WUF6); in LL_PWR_ClearFlag_WU6()
1924 WRITE_REG(PWR->SR1, PWR_SR1_WUF7); in LL_PWR_ClearFlag_WU7()
1934 WRITE_REG(PWR->SR1, PWR_SR1_WUF8); in LL_PWR_ClearFlag_WU8()
1944 WRITE_REG(PWR->SR1, PWR_SR1_WUF9); in LL_PWR_ClearFlag_WU9()
1954 WRITE_REG(PWR->SR1, PWR_SR1_WUF10); in LL_PWR_ClearFlag_WU10()
1964 WRITE_REG(PWR->SR1, PWR_SR1_WUF11); in LL_PWR_ClearFlag_WU11()
1974 WRITE_REG(PWR->SR3, PWR_SR3_WUF12); in LL_PWR_ClearFlag_WU12()
1984 WRITE_REG(PWR->SR3, PWR_SR3_WUF13); in LL_PWR_ClearFlag_WU13()
1994 WRITE_REG(PWR->SR3, PWR_SR3_WUF14); in LL_PWR_ClearFlag_WU14()
2004 WRITE_REG(PWR->SR3, PWR_SR3_WUF15); in LL_PWR_ClearFlag_WU15()
2014 WRITE_REG(PWR->SR3, PWR_SR3_WUF16); in LL_PWR_ClearFlag_WU16()
2024 WRITE_REG(PWR->SR3, PWR_SR3_WUF17); in LL_PWR_ClearFlag_WU17()
2034 WRITE_REG(PWR->SR3, PWR_SR3_WUF18); in LL_PWR_ClearFlag_WU18()
2044 WRITE_REG(PWR->SR3, PWR_SR3_WUF19); in LL_PWR_ClearFlag_WU19()
2055 WRITE_REG(PWR->SR3, PWR_SR3_WUF20); in LL_PWR_ClearFlag_WU20()
2067 WRITE_REG(PWR->SR3, PWR_SR3_WUF21); in LL_PWR_ClearFlag_WU21()
2079 WRITE_REG(PWR->SR3, PWR_SR3_WUF22); in LL_PWR_ClearFlag_WU22()
2091 WRITE_REG(PWR->SR3, PWR_SR3_WUF23); in LL_PWR_ClearFlag_WU23()
2103 WRITE_REG(PWR->SR3, PWR_SR3_WUF24); in LL_PWR_ClearFlag_WU24()
2115 WRITE_REG(PWR->SR3, PWR_SR3_WUF25); in LL_PWR_ClearFlag_WU25()
2127 WRITE_REG(PWR->SR3, PWR_SR3_WUF26); in LL_PWR_ClearFlag_WU26()
2139 WRITE_REG(PWR->SR3, PWR_SR3_WUF27); in LL_PWR_ClearFlag_WU27()
2158 return ((READ_BIT(PWR->SR1, PWR_SR1_WBLEHCPUF) == (PWR_SR1_WBLEHCPUF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WBLEHCPUF()
2168 return ((READ_BIT(PWR->SR1, PWR_SR1_WBLEF) == (PWR_SR1_WBLEF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WBLEF()
2178 WRITE_REG(PWR->SR1, PWR_SR1_WBLEHCPUF); in LL_PWR_ClearFlag_WBLEHCPUF()
2188 WRITE_REG(PWR->SR1, PWR_SR1_WBLEF); in LL_PWR_ClearFlag_WBLEF()
2206 return ((READ_BIT(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF) == (PWR_EXTSRR_RFPHASEF)) ? 1UL : 0UL); in LL_PWR_GetRFWakeupFlag()
2216 WRITE_REG(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF); in LL_PWR_ClearRFWakeupFlag()
2226 return ((READ_BIT(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF) == (PWR_EXTSRR_DEEPSTOPF)) ? 1UL : 0UL); in LL_PWR_GetDeepstopSeqFlag()
2236 WRITE_REG(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF); in LL_PWR_ClearDeepstopSeqFlag()
2259 return ((READ_BIT(PWR->SR2, IO) == (IO)) ? 1UL : 0UL); in LL_PWR_GetIOBootVal()
2269 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
2280 return ((READ_BIT(PWR->SR2, PWR_SR2_REGMS) == (PWR_SR2_REGMS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGMS()
2291 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPS()
2304 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) == (PWR_SR2_SMPSRDY)) ? 1UL : 0UL); in LL_PWR_IsSMPSReady()
2314 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSENR) == (PWR_SR2_SMPSENR)) ? 1UL : 0UL); in LL_PWR_IsSMPSinRUNMode()
2324 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSBYPR) == (PWR_SR2_SMPSBYPR)) ? 1UL : 0UL); in LL_PWR_IsSMPSinPRECHARGEMode()
2337 MODIFY_REG(PWR->CR5, PWR_CR5_NOSMPS, mode); in LL_PWR_SetSMPSMode()
2349 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_NOSMPS)); in LL_PWR_GetSMPSMode()
2362 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSFBYP, mode); in LL_PWR_SetSMPSPrechargeMode()
2372 return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSFBYP) == (PWR_CR5_SMPSFBYP)) ? 1UL : 0UL); in LL_PWR_IsEnabledSMPSPrechargeMode()
2385 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSLPOPEN, mode); in LL_PWR_SetSMPSOpenMode()
2400 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSBOMSEL, BOM); in LL_PWR_SetSMPSBOM()
2414 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSBOMSEL)); in LL_PWR_GetSMPSBOM()
2441 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSLVL, OutputVoltageLevel); in LL_PWR_SMPS_SetOutputVoltageLevel()
2468 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSLVL)); in LL_PWR_SMPS_GetOutputVoltageLevel()
2696 CLEAR_BIT(PWR->PUCRA, GPIONumber); in LL_PWR_SetNoPullA()
2697 CLEAR_BIT(PWR->PDCRA, GPIONumber); in LL_PWR_SetNoPullA()
2725 CLEAR_BIT(PWR->PUCRB, GPIONumber); in LL_PWR_SetNoPullB()
2726 CLEAR_BIT(PWR->PDCRB, GPIONumber); in LL_PWR_SetNoPullB()
2742 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG4, mode); in LL_PWR_SetPA4OutputinDEEPSTOP()
2756 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG4) >> PWR_IOxCFG_IOCFG4_Pos); in LL_PWR_GetPA4OutputinDEEPSTOP()
2773 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG5, mode); in LL_PWR_SetPA5OutputinDEEPSTOP()
2787 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG5) >> PWR_IOxCFG_IOCFG5_Pos); in LL_PWR_GetPA5OutputinDEEPSTOP()
2804 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG6, mode); in LL_PWR_SetPA6OutputinDEEPSTOP()
2818 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG6) >> PWR_IOxCFG_IOCFG6_Pos); in LL_PWR_GetPA6OutputinDEEPSTOP()
2835 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG7, mode); in LL_PWR_SetPA7OutputinDEEPSTOP()
2849 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG7) >> PWR_IOxCFG_IOCFG7_Pos); in LL_PWR_GetPA7OutputinDEEPSTOP()
2866 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG0, mode); in LL_PWR_SetPA8OutputinDEEPSTOP()
2880 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG0) >> PWR_IOxCFG_IOCFG0_Pos); in LL_PWR_GetPA8OutputinDEEPSTOP()
2897 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG1, mode); in LL_PWR_SetPA9OutputinDEEPSTOP()
2911 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG1) >> PWR_IOxCFG_IOCFG1_Pos); in LL_PWR_GetPA9OutputinDEEPSTOP()
2928 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG2, mode); in LL_PWR_SetPA10OutputinDEEPSTOP()
2942 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG2) >> PWR_IOxCFG_IOCFG2_Pos); in LL_PWR_GetPA10OutputinDEEPSTOP()
2959 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG3, mode); in LL_PWR_SetPA11OutputinDEEPSTOP()
2973 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG3) >> PWR_IOxCFG_IOCFG3_Pos); in LL_PWR_GetPA11OutputinDEEPSTOP()
2985 …MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_SMPS_TRIM, ((trim << PWR_ENGTRIM_SMPS_TRIM_Pos) & PWR_ENGTRIM… in LL_PWR_SetSMPSTrim()
2986 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_SMPSTRIMEN); in LL_PWR_SetSMPSTrim()
2996 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_SMPSTRIMEN)) in LL_PWR_GetSMPSTrim()
2998 return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_SMPS_TRIM) >> PWR_ENGTRIM_SMPS_TRIM_Pos); in LL_PWR_GetSMPSTrim()
3002 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_SMPS_TRIM) >> PWR_TRIMR_SMPS_TRIM_Pos); in LL_PWR_GetSMPSTrim()
3014 …MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_MR, ((trim << PWR_ENGTRIM_TRIM_MR_Pos) & PWR_ENGTRIM_TRI… in LL_PWR_SetMRTrim()
3015 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMMREN); in LL_PWR_SetMRTrim()
3025 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMMREN)) in LL_PWR_GetMRTrim()
3027 return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_MR) >> PWR_ENGTRIM_TRIM_MR_Pos); in LL_PWR_GetMRTrim()
3031 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_TRIM_MR) >> PWR_TRIMR_TRIM_MR_Pos); in LL_PWR_GetMRTrim()
3044 …MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_LSI_LPMU, ((trim << PWR_ENGTRIM_TRIM_LSI_LPMU_Pos) & PWR… in LL_PWR_SetLSILPMUTrim()
3045 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMLSILPMUEN); in LL_PWR_SetLSILPMUTrim()
3055 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMLSILPMUEN)) in LL_PWR_GetLSILPMUTrim()
3057 …return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_LSI_LPMU) >> PWR_ENGTRIM_TRIM_LSI_LPMU_P… in LL_PWR_GetLSILPMUTrim()
3061 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_TRIM_LSI_LPMU) >> PWR_TRIMR_TRIM_LSI_LPMU_Pos); in LL_PWR_GetLSILPMUTrim()
3075 …MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_RFDREG, ((trim << PWR_ENGTRIM_TRIM_RFDREG_Pos) & PWR_ENG… in LL_PWR_SetRFDREGTrim()
3076 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMRFDREGEN); in LL_PWR_SetRFDREGTrim()
3086 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMRFDREGEN)) in LL_PWR_GetRFDREGTrim()
3088 … return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_RFDREG) >> PWR_ENGTRIM_TRIM_RFDREG_Pos); in LL_PWR_GetRFDREGTrim()
3092 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_RFD_REG_TRIM) >> PWR_TRIMR_RFD_REG_TRIM_Pos); in LL_PWR_GetRFDREGTrim()
3109 SET_BIT(PWR->DBGR, PWR_DBGR_DEEPSTOP2); in LL_PWR_EnableDEEPSTOP2()
3119 CLEAR_BIT(PWR->DBGR, PWR_DBGR_DEEPSTOP2); in LL_PWR_DisableDEEPSTOP2()
3129 return ((READ_BIT(PWR->DBGR, PWR_DBGR_DEEPSTOP2) == (PWR_DBGR_DEEPSTOP2)) ? 1UL : 0UL); in LL_PWR_IsEnabledDEEPSTOP2()
3148 MODIFY_REG(PWR->CR5, PWR_CR5_SMPS_PRECH_CUR_SEL, mode); in LL_PWR_SetSMPSPrechargeLimitCurrent()
3162 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPS_PRECH_CUR_SEL)); in LL_PWR_GetSMPSPrechargeLimitCurrent()
3174 SET_BIT(PWR->SDWN_WUEN, PWR_SDWN_WUEN_WUEN); in LL_PWR_EnableIOWakeupSDN()
3184 CLEAR_BIT(PWR->SDWN_WUEN, PWR_SDWN_WUEN_WUEN); in LL_PWR_DisableIOWakeupSDN()
3194 return ((READ_BIT(PWR->SDWN_WUEN, PWR_SDWN_WUEN_WUEN) == (PWR_SDWN_WUEN_WUEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledIOWakeupSDN()
3209 CLEAR_BIT(PWR->SDWN_WUPOL, PWR_SDWN_WUPOL_WUPOL); in LL_PWR_IOWakeupPolaritySDN()
3213 SET_BIT(PWR->SDWN_WUPOL, PWR_SDWN_WUPOL_WUPOL); in LL_PWR_IOWakeupPolaritySDN()
3224 return ((READ_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF) == (PWR_SDWN_WUF_WUF)) ? 1UL : 0UL); in LL_PWR_IsIOWakeupSDN()
3234 CLEAR_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF); in LL_PWR_ClearIOWakeupFlagSDN()