2742   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG4, mode);  in LL_PWR_SetPA4OutputinDEEPSTOP()
2756   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG4) >> PWR_IOxCFG_IOCFG4_Pos);  in LL_PWR_GetPA4OutputinDEEPSTOP()
2773   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG5, mode);  in LL_PWR_SetPA5OutputinDEEPSTOP()
2787   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG5) >> PWR_IOxCFG_IOCFG5_Pos);  in LL_PWR_GetPA5OutputinDEEPSTOP()
2804   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG6, mode);  in LL_PWR_SetPA6OutputinDEEPSTOP()
2818   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG6) >> PWR_IOxCFG_IOCFG6_Pos);  in LL_PWR_GetPA6OutputinDEEPSTOP()
2835   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG7, mode);  in LL_PWR_SetPA7OutputinDEEPSTOP()
2849   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG7) >> PWR_IOxCFG_IOCFG7_Pos);  in LL_PWR_GetPA7OutputinDEEPSTOP()
2866   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG0, mode);  in LL_PWR_SetPA8OutputinDEEPSTOP()
2880   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG0) >> PWR_IOxCFG_IOCFG0_Pos);  in LL_PWR_GetPA8OutputinDEEPSTOP()
2897   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG1, mode);  in LL_PWR_SetPA9OutputinDEEPSTOP()
2911   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG1) >> PWR_IOxCFG_IOCFG1_Pos);  in LL_PWR_GetPA9OutputinDEEPSTOP()
2928   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG2, mode);  in LL_PWR_SetPA10OutputinDEEPSTOP()
2942   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG2) >> PWR_IOxCFG_IOCFG2_Pos);  in LL_PWR_GetPA10OutputinDEEPSTOP()
2959   MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG3, mode);  in LL_PWR_SetPA11OutputinDEEPSTOP()
2973   return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG3) >> PWR_IOxCFG_IOCFG3_Pos);  in LL_PWR_GetPA11OutputinDEEPSTOP()