Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
61 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Tr…
62 …SecureFault_IRQn = -9, /*!< -9 Secure Fault …
63 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
64 …DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor …
65 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
66 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
71 …RTC_IRQn = 2, /*!< RTC non-secure interrupt …
75 …FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt …
185 /* ------- Start of section using anonymous unions and disabling warnings ------- */
193 #pragma clang diagnostic ignored "-Wc11-extensions"
194 #pragma clang diagnostic ignored "-Wreserved-id-macro"
207 /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
219 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
251 * @brief Inter-integrated Circuit Interface
276 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
277 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
278 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
279 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
280 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
281 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
282 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
283 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
284 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
317 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
320 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
321 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
329 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
355 uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */
393 …__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: …
394 …VED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
398 …VED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
406 …VED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
407 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: …
422 …2_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */
423 …2_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
425 …2_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */
437 …__IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offse…
441 …__IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offse…
442 …__IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offse…
443 …__IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offse…
445 …__IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offse…
449 …RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */
451 …__IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offse…
452 …__IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offse…
466 …__IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offse…
467 …RESERVED4[7]; /*!< Reserved4, Address offset: 0x84-0x9C */
468 …__IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offse…
469 …RESERVED5[7]; /*!< Reserved5, Address offset: 0xA4-0xBC */
472 …RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */
473 …__IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offse…
474 …RESERVED7[7]; /*!< Reserved7, Address offset: 0xD4-0xEC */
475 …__IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offse…
501 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
506 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
508 …__IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
518 … Reserved1, Address offset: 0x04-0x0C */
526 … Reserved3, Address offset: 0x2C-0x3C */
527 …__IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, …
528 …__IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, …
529 …__IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, …
530 …__IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, …
531 …__IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, …
532 …__IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, …
533 …__IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, …
534 …__IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, …
535 …__IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, …
536 …__IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, …
537 … Reserved4, Address offset: 0x68-0x6C */
538 …__IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, …
539 …__IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, …
540 … Reserved5, Address offset: 0x78-0x7C */
541 …__IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, …
542 …__IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, …
543 …__IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, …
544 …__IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, …
550 … RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
552 … RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */
553 …t32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */
554 … RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */
555 …t32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
585 …uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C …
603 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
621 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
641 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
647 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
721 …uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C …
736 …__IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset:…
748 …uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 …
765 …RVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
768 …RVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
774 …RVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
780 …RVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
786 …RVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
788 …RVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
790 …RVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
796 …RVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
798 …RVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
804 …RVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
806 …RVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
840 …__IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x…
841 …__IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x…
842 …__IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x…
843 …__IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x…
844 …__IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x…
845 …__IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x…
846 …__IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x…
847 …__IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x…
848 …__IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x…
849 …__IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x…
850 …32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x78-0x7C */
851 …__IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x…
852 …__IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x…
853 …__IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x…
854 …__IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x…
954 * @brief Real-Time Clock
972 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
1009 …_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */
1011 …_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */
1097 …__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset…
1130 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1137 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
1202 …[4]; /*!< Reserved, 0x030 - 0x03C */
1211 …[8]; /*!< Reserved, 0x060 - 0x07C */
1220 …[8]; /*!< Reserved, 0x0A0 - 0x0BC */
1240 …[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
1242 …[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
1269 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address of…
1282 …uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C …
1288 …uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C …
1293 …uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C …
1355 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1357 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1383 …XCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
1399 /* -------- End of section using anonymous unions and disabling warnings -------- */
1433 /* External memories base addresses - Not aliased */
1437 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1438 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (512 KB) non-secure base address …
1439 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address …
1440 #define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address …
1441 #define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address …
1442 #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address …
1444 /* Peripheral memory map - Non secure */
1586 /* Flash, Peripheral and internal SRAMs base addresses - Secure */
1593 /* Peripheral memory map - Secure */
1743 #define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address …
1744 #define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) …
1783 * @brief RSSLib non-secure callable function pointer structure
2089 /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
3637 #define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off m…
4403 … ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */
4437 … ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
4589 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data regist…
4897 …R DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
4900 … DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
4905 …R DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
4908 …RB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data…
4913 …R DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
4916 …RB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned dat…
4921 …R DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
4924 … DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
4929 …R DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
4932 …RB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data…
4937 …R DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
4940 …RB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned dat…
4945 …R DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
4948 …R DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
4953 …R DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
4956 …R DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
4961 …R DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
4964 …R DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
5709 … DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */
5712 … DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */
5715 … DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */
5718 … DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */
5721 … DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */
5724 … DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */
5727 … DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */
5730 … DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */
5733 … DMA_MISR_MIS8_Msk /*!< Masked Interrupt State of Non-Secure Channel 8 */
5736 … DMA_MISR_MIS9_Msk /*!< Masked Interrupt State of Non-Secure Channel 9 */
5739 … DMA_MISR_MIS10_Msk /*!< Masked Interrupt State of Non-Secure Channel 10 */
5742 … DMA_MISR_MIS11_Msk /*!< Masked Interrupt State of Non-Secure Channel 11 */
5745 … DMA_MISR_MIS12_Msk /*!< Masked Interrupt State of Non-Secure Channel 12 */
5748 … DMA_MISR_MIS13_Msk /*!< Masked Interrupt State of Non-Secure Channel 13 */
5751 … DMA_MISR_MIS14_Msk /*!< Masked Interrupt State of Non-Secure Channel 14 */
5754 … DMA_MISR_MIS14_Msk /*!< Masked Interrupt State of Non-Secure Channel 15 */
5809 #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-lis…
5823 … DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag …
5849 … DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag …
5884 … DMA_CCR_ULEIE_Msk /*!< Update linked-list item error inter…
5899 #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-lis…
5925 …k /*!< Source byte exchange within the unaligned half-word of each source w…
5948 … DMA_CTR1_DHX_Msk /*!< Destination half-word exchange …
6037 … DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
6905 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of…
7303 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-…
7306 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-…
7473 #define FLASH_BLOCKBASED_NB_REG (1U) /*!< 1 Block-based register for…
7510 #define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power …
7513 …1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */
7516 …2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */
7519 …PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during slee…
7524 #define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure…
7527 #define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure…
7530 #define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure…
7533 #define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure…
7536 #define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure…
7539 #define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure…
7542 #define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure…
7548 #define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure…
7551 #define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure…
7560 …_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */
7563 …_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */
7597 #define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure…
7600 #define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure…
7603 #define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure…
7606 #define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure…
7609 #define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure…
7612 #define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure…
7615 #define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure…
7618 #define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure…
7624 #define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure…
7627 #define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure…
7636 #define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure…
7679 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail a…
7682 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail b…
7685 …ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
7752 #define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank …
7770 #define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-…
7784 #define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure…
7789 #define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure…
7889 … FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
7902 … FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
7913 …UF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
7921 …F_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
9614 #define MDF_DFLTRSFR_HPFBYP MDF_DFLTRSFR_HPFBYP_Msk /*!<High-pass f…
9617 …C MDF_DFLTRSFR_HPFC_Msk /*!<High-pass filter cut-off frequency…
9886 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
9891 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload…
10167 …1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
10188 …2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
10203 /*----------------------------------------------------------------------------*/
10237 …3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
10258 …4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
10273 /*----------------------------------------------------------------------------*/
10302 …5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
10318 …6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
10411 …ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
10460 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
10476 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State S…
10479 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State S…
10506 …BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
10509 …K2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
10724 … LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
10727 … LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
10768 … LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
10771 … LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
10811 … LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt ena…
10814 … LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt ena…
11298 …AIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
11380 …LIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable …
11383 …FAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable …
11434 … SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
12386 … PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection …
12398 #define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-…
12401 … PWR_CR1_SRAM1PD_Msk /*!< SRAM1 power-down in Run mode …
12404 … PWR_CR1_SRAM2PD_Msk /*!< SRAM2 power-down in Run mode …
12407 … PWR_CR1_SRAM4PD_Msk /*!< SRAM4 power-down in Run mode …
12412 … PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 page 1 (64 KB) power-down in Stop modes (S…
12415 … PWR_CR2_SRAM1PDS2_Msk /*!< SRAM1 page 2 (64 KB) power-down in Stop modes (S…
12418 … PWR_CR2_SRAM1PDS3_Msk /*!< SRAM1 page 3 (64 KB) power-down in Stop modes (S…
12421 … PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 page 1 (8 KB) power-down in Stop modes (S…
12424 … PWR_CR2_SRAM2PDS2_Msk /*!< SRAM2 page 2 (56 KB) power-down in Stop modes (S…
12427 … PWR_CR2_SRAM4PDS_Msk /*!< SRAM4 power-down in Stop modes (S…
12430 … PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes (S…
12433 … PWR_CR2_DC1RAMPDS_Msk /*!< DCACHE1 SRAM power-down in Stop modes (S…
12436 …R2_PRAMPDS_Msk /*!< FDCAN and USB peripherals SRAM power-down in Stop modes (S…
12439 #define PWR_CR2_SRAM4FWU PWR_CR2_SRAM4FWU_Msk /*!< SRAM4 fast…
12442 … PWR_CR2_FLASHFWU_Msk /*!< Flash memory fast wakeup from Stop mo…
12453 #define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft …
12646 #define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Low-power …
12655 …PCSEC PWR_SECCFGR_APCSEC_Msk /*!< Pull-up/pull-down secure prote…
12663 #define PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk /*!< RCC non-se…
12776 … PWR_APCR_APC_Msk /*!< Apply pull-up and pull-down configurat…
12781 …RA_PU0 PWR_PUCRA_PU0_Msk /*!< Apply pull-up for PA0 */
12784 …RA_PU1 PWR_PUCRA_PU1_Msk /*!< Apply pull-up for PA1 */
12787 …RA_PU2 PWR_PUCRA_PU2_Msk /*!< Apply pull-up for PA2 */
12790 …RA_PU3 PWR_PUCRA_PU3_Msk /*!< Apply pull-up for PA3 */
12793 …RA_PU4 PWR_PUCRA_PU4_Msk /*!< Apply pull-up for PA4 */
12796 …RA_PU5 PWR_PUCRA_PU5_Msk /*!< Apply pull-up for PA5 */
12799 …RA_PU6 PWR_PUCRA_PU6_Msk /*!< Apply pull-up for PA6 */
12802 …RA_PU7 PWR_PUCRA_PU7_Msk /*!< Apply pull-up for PA7 */
12805 …RA_PU8 PWR_PUCRA_PU8_Msk /*!< Apply pull-up for PA8 */
12808 …RA_PU9 PWR_PUCRA_PU9_Msk /*!< Apply pull-up for PA9 */
12811 …RA_PU10 PWR_PUCRA_PU10_Msk /*!< Apply pull-up for PA10 */
12814 …RA_PU11 PWR_PUCRA_PU11_Msk /*!< Apply pull-up for PA11 */
12817 …RA_PU12 PWR_PUCRA_PU12_Msk /*!< Apply pull-up for PA12 */
12820 …RA_PU13 PWR_PUCRA_PU13_Msk /*!< Apply pull-up for PA13 */
12823 …RA_PU15 PWR_PUCRA_PU15_Msk /*!< Apply pull-up for PA15 */
12828 …_PD0 PWR_PDCRA_PD0_Msk /*!< Apply pull-down for PA0 */
12831 …_PD1 PWR_PDCRA_PD1_Msk /*!< Apply pull-down for PA1 */
12834 …_PD2 PWR_PDCRA_PD2_Msk /*!< Apply pull-down for PA2 */
12837 …_PD3 PWR_PDCRA_PD3_Msk /*!< Apply pull-down for PA3 */
12840 …_PD4 PWR_PDCRA_PD4_Msk /*!< Apply pull-down for PA4 */
12843 …_PD5 PWR_PDCRA_PD5_Msk /*!< Apply pull-down for PA5 */
12846 …_PD6 PWR_PDCRA_PD6_Msk /*!< Apply pull-down for PA6 */
12849 …_PD7 PWR_PDCRA_PD7_Msk /*!< Apply pull-down for PA7 */
12852 …_PD8 PWR_PDCRA_PD8_Msk /*!< Apply pull-down for PA8 */
12855 …_PD9 PWR_PDCRA_PD9_Msk /*!< Apply pull-down for PA9 */
12858 …_PD10 PWR_PDCRA_PD10_Msk /*!< Apply pull-down for PA10 */
12861 …_PD11 PWR_PDCRA_PD11_Msk /*!< Apply pull-down for PA11 */
12864 …_PD12 PWR_PDCRA_PD12_Msk /*!< Apply pull-down for PA12 */
12867 …_PD14 PWR_PDCRA_PD14_Msk /*!< Apply pull-down for PA14 */
12872 …RB_PU0 PWR_PUCRB_PU0_Msk /*!< Apply pull-up for PB0 */
12875 …RB_PU1 PWR_PUCRB_PU1_Msk /*!< Apply pull-up for PB1 */
12878 …RB_PU2 PWR_PUCRB_PU2_Msk /*!< Apply pull-up for PB2 */
12881 …RB_PU3 PWR_PUCRB_PU3_Msk /*!< Apply pull-up for PB3 */
12884 …RB_PU4 PWR_PUCRB_PU4_Msk /*!< Apply pull-up for PB4 */
12887 …RB_PU5 PWR_PUCRB_PU5_Msk /*!< Apply pull-up for PB5 */
12890 …RB_PU6 PWR_PUCRB_PU6_Msk /*!< Apply pull-up for PB6 */
12893 …RB_PU7 PWR_PUCRB_PU7_Msk /*!< Apply pull-up for PB7 */
12896 …RB_PU8 PWR_PUCRB_PU8_Msk /*!< Apply pull-up for PB8 */
12899 …RB_PU9 PWR_PUCRB_PU9_Msk /*!< Apply pull-up for PB9 */
12902 …RB_PU10 PWR_PUCRB_PU10_Msk /*!< Apply pull-up for PB10 */
12905 …RB_PU11 PWR_PUCRB_PU11_Msk /*!< Apply pull-up for PB11 */
12908 …RB_PU12 PWR_PUCRB_PU12_Msk /*!< Apply pull-up for PB12 */
12911 …RB_PU13 PWR_PUCRB_PU13_Msk /*!< Apply pull-up for PB13 */
12914 …RB_PU14 PWR_PUCRB_PU14_Msk /*!< Apply pull-up for PB14 */
12917 …RB_PU15 PWR_PUCRB_PU15_Msk /*!< Apply pull-up for PB15 */
12922 …_PD0 PWR_PDCRB_PD0_Msk /*!< Apply pull-down for PB0 */
12925 …_PD1 PWR_PDCRB_PD1_Msk /*!< Apply pull-down for PB1 */
12928 …_PD2 PWR_PDCRB_PD2_Msk /*!< Apply pull-down for PB2 */
12931 …_PD3 PWR_PDCRB_PD3_Msk /*!< Apply pull-down for PB3 */
12934 …_PD5 PWR_PDCRB_PD5_Msk /*!< Apply pull-down for PB5 */
12937 …_PD6 PWR_PDCRB_PD6_Msk /*!< Apply pull-down for PB6 */
12940 …_PD7 PWR_PDCRB_PD7_Msk /*!< Apply pull-down for PB7 */
12943 …_PD8 PWR_PDCRB_PD8_Msk /*!< Apply pull-down for PB8 */
12946 …_PD9 PWR_PDCRB_PD9_Msk /*!< Apply pull-down for PB9 */
12949 …_PD10 PWR_PDCRB_PD10_Msk /*!< Apply pull-down for PB10 */
12952 …_PD11 PWR_PDCRB_PD11_Msk /*!< Apply pull-down for PB11 */
12955 …_PD12 PWR_PDCRB_PD12_Msk /*!< Apply pull-down for PB12 */
12958 …_PD13 PWR_PDCRB_PD13_Msk /*!< Apply pull-down for PB13 */
12961 …_PD14 PWR_PDCRB_PD14_Msk /*!< Apply pull-down for PB14 */
12964 …_PD15 PWR_PDCRB_PD15_Msk /*!< Apply pull-down for PB15 */
12969 …RC_PU0 PWR_PUCRC_PU0_Msk /*!< Apply pull-up for PC0 */
12972 …RC_PU1 PWR_PUCRC_PU1_Msk /*!< Apply pull-up for PC1 */
12975 …RC_PU2 PWR_PUCRC_PU2_Msk /*!< Apply pull-up for PC2 */
12978 …RC_PU3 PWR_PUCRC_PU3_Msk /*!< Apply pull-up for PC3 */
12981 …RC_PU4 PWR_PUCRC_PU4_Msk /*!< Apply pull-up for PC4 */
12984 …RC_PU5 PWR_PUCRC_PU5_Msk /*!< Apply pull-up for PC5 */
12987 …RC_PU6 PWR_PUCRC_PU6_Msk /*!< Apply pull-up for PC6 */
12990 …RC_PU7 PWR_PUCRC_PU7_Msk /*!< Apply pull-up for PC7 */
12993 …RC_PU8 PWR_PUCRC_PU8_Msk /*!< Apply pull-up for PC8 */
12996 …RC_PU9 PWR_PUCRC_PU9_Msk /*!< Apply pull-up for PC9 */
12999 …RC_PU10 PWR_PUCRC_PU10_Msk /*!< Apply pull-up for PC10 */
13002 …RC_PU11 PWR_PUCRC_PU11_Msk /*!< Apply pull-up for PC11 */
13005 …RC_PU12 PWR_PUCRC_PU12_Msk /*!< Apply pull-up for PC12 */
13008 …RC_PU13 PWR_PUCRC_PU13_Msk /*!< Apply pull-up for PC13 */
13011 …RC_PU14 PWR_PUCRC_PU14_Msk /*!< Apply pull-up for PC14 */
13014 …RC_PU15 PWR_PUCRC_PU15_Msk /*!< Apply pull-up for PC15 */
13019 …_PD0 PWR_PDCRC_PD0_Msk /*!< Apply pull-down for PC0 */
13022 …_PD1 PWR_PDCRC_PD1_Msk /*!< Apply pull-down for PC1 */
13025 …_PD2 PWR_PDCRC_PD2_Msk /*!< Apply pull-down for PC2 */
13028 …_PD3 PWR_PDCRC_PD3_Msk /*!< Apply pull-down for PC3 */
13031 …_PD4 PWR_PDCRC_PD4_Msk /*!< Apply pull-down for PC4 */
13034 …_PD5 PWR_PDCRC_PD5_Msk /*!< Apply pull-down for PC5 */
13037 …_PD6 PWR_PDCRC_PD6_Msk /*!< Apply pull-down for PC6 */
13040 …_PD7 PWR_PDCRC_PD7_Msk /*!< Apply pull-down for PC7 */
13043 …_PD8 PWR_PDCRC_PD8_Msk /*!< Apply pull-down for PC8 */
13046 …_PD9 PWR_PDCRC_PD9_Msk /*!< Apply pull-down for PC9 */
13049 …_PD10 PWR_PDCRC_PD10_Msk /*!< Apply pull-down for PC10 */
13052 …_PD11 PWR_PDCRC_PD11_Msk /*!< Apply pull-down for PC11 */
13055 …_PD12 PWR_PDCRC_PD12_Msk /*!< Apply pull-down for PC12 */
13058 …_PD13 PWR_PDCRC_PD13_Msk /*!< Apply pull-down for PC13 */
13061 …_PD14 PWR_PDCRC_PD14_Msk /*!< Apply pull-down for PC14 */
13064 …_PD15 PWR_PDCRC_PD15_Msk /*!< Apply pull-down for PC15 */
13069 …RD_PU0 PWR_PUCRD_PU0_Msk /*!< Apply pull-up for PD0 */
13072 …RD_PU1 PWR_PUCRD_PU1_Msk /*!< Apply pull-up for PD1 */
13075 …RD_PU2 PWR_PUCRD_PU2_Msk /*!< Apply pull-up for PD2 */
13078 …RD_PU3 PWR_PUCRD_PU3_Msk /*!< Apply pull-up for PD3 */
13081 …RD_PU4 PWR_PUCRD_PU4_Msk /*!< Apply pull-up for PD4 */
13084 …RD_PU5 PWR_PUCRD_PU5_Msk /*!< Apply pull-up for PD5 */
13087 …RD_PU6 PWR_PUCRD_PU6_Msk /*!< Apply pull-up for PD6 */
13090 …RD_PU7 PWR_PUCRD_PU7_Msk /*!< Apply pull-up for PD7 */
13093 …RD_PU8 PWR_PUCRD_PU8_Msk /*!< Apply pull-up for PD8 */
13096 …RD_PU9 PWR_PUCRD_PU9_Msk /*!< Apply pull-up for PD9 */
13099 …RD_PU10 PWR_PUCRD_PU10_Msk /*!< Apply pull-up for PD10 */
13102 …RD_PU11 PWR_PUCRD_PU11_Msk /*!< Apply pull-up for PD11 */
13105 …RD_PU12 PWR_PUCRD_PU12_Msk /*!< Apply pull-up for PD12 */
13108 …RD_PU13 PWR_PUCRD_PU13_Msk /*!< Apply pull-up for PD13 */
13111 …RD_PU14 PWR_PUCRD_PU14_Msk /*!< Apply pull-up for PD14 */
13114 …RD_PU15 PWR_PUCRD_PU15_Msk /*!< Apply pull-up for PD15 */
13119 …_PD0 PWR_PDCRD_PD0_Msk /*!< Apply pull-down for PD0 */
13122 …_PD1 PWR_PDCRD_PD1_Msk /*!< Apply pull-down for PD1 */
13125 …_PD2 PWR_PDCRD_PD2_Msk /*!< Apply pull-down for PD2 */
13128 …_PD3 PWR_PDCRD_PD3_Msk /*!< Apply pull-down for PD3 */
13131 …_PD4 PWR_PDCRD_PD4_Msk /*!< Apply pull-down for PD4 */
13134 …_PD5 PWR_PDCRD_PD5_Msk /*!< Apply pull-down for PD5 */
13137 …_PD6 PWR_PDCRD_PD6_Msk /*!< Apply pull-down for PD6 */
13140 …_PD7 PWR_PDCRD_PD7_Msk /*!< Apply pull-down for PD7 */
13143 …_PD8 PWR_PDCRD_PD8_Msk /*!< Apply pull-down for PD8 */
13146 …_PD9 PWR_PDCRD_PD9_Msk /*!< Apply pull-down for PD9 */
13149 …_PD10 PWR_PDCRD_PD10_Msk /*!< Apply pull-down for PD10 */
13152 …_PD11 PWR_PDCRD_PD11_Msk /*!< Apply pull-down for PD11 */
13155 …_PD12 PWR_PDCRD_PD12_Msk /*!< Apply pull-down for PD12 */
13158 …_PD13 PWR_PDCRD_PD13_Msk /*!< Apply pull-down for PD13 */
13161 …_PD14 PWR_PDCRD_PD14_Msk /*!< Apply pull-down for PD14 */
13164 …_PD15 PWR_PDCRD_PD15_Msk /*!< Apply pull-down for PD15 */
13169 …RE_PU0 PWR_PUCRE_PU0_Msk /*!< Apply pull-up for PE0 */
13172 …RE_PU1 PWR_PUCRE_PU1_Msk /*!< Apply pull-up for PE1 */
13175 …RE_PU2 PWR_PUCRE_PU2_Msk /*!< Apply pull-up for PE2 */
13178 …RE_PU3 PWR_PUCRE_PU3_Msk /*!< Apply pull-up for PE3 */
13181 …RE_PU4 PWR_PUCRE_PU4_Msk /*!< Apply pull-up for PE4 */
13184 …RE_PU5 PWR_PUCRE_PU5_Msk /*!< Apply pull-up for PE5 */
13187 …RE_PU6 PWR_PUCRE_PU6_Msk /*!< Apply pull-up for PE6 */
13190 …RE_PU7 PWR_PUCRE_PU7_Msk /*!< Apply pull-up for PE7 */
13193 …RE_PU8 PWR_PUCRE_PU8_Msk /*!< Apply pull-up for PE8 */
13196 …RE_PU9 PWR_PUCRE_PU9_Msk /*!< Apply pull-up for PE9 */
13199 …RE_PU10 PWR_PUCRE_PU10_Msk /*!< Apply pull-up for PE10 */
13202 …RE_PU11 PWR_PUCRE_PU11_Msk /*!< Apply pull-up for PE11 */
13205 …RE_PU12 PWR_PUCRE_PU12_Msk /*!< Apply pull-up for PE12 */
13208 …RE_PU13 PWR_PUCRE_PU13_Msk /*!< Apply pull-up for PE13 */
13211 …RE_PU14 PWR_PUCRE_PU14_Msk /*!< Apply pull-up for PE14 */
13214 …RE_PU15 PWR_PUCRE_PU15_Msk /*!< Apply pull-up for PE15 */
13219 …_PD0 PWR_PDCRE_PD0_Msk /*!< Apply pull-down for PE0 */
13222 …_PD1 PWR_PDCRE_PD1_Msk /*!< Apply pull-down for PE1 */
13225 …_PD2 PWR_PDCRE_PD2_Msk /*!< Apply pull-down for PE2 */
13228 …_PD3 PWR_PDCRE_PD3_Msk /*!< Apply pull-down for PE3 */
13231 …_PD4 PWR_PDCRE_PD4_Msk /*!< Apply pull-down for PE4 */
13234 …_PD5 PWR_PDCRE_PD5_Msk /*!< Apply pull-down for PE5 */
13237 …_PD6 PWR_PDCRE_PD6_Msk /*!< Apply pull-down for PE6 */
13240 …_PD7 PWR_PDCRE_PD7_Msk /*!< Apply pull-down for PE7 */
13243 …_PD8 PWR_PDCRE_PD8_Msk /*!< Apply pull-down for PE8 */
13246 …_PD9 PWR_PDCRE_PD9_Msk /*!< Apply pull-down for PE9 */
13249 …_PD10 PWR_PDCRE_PD10_Msk /*!< Apply pull-down for PE10 */
13252 …_PD11 PWR_PDCRE_PD11_Msk /*!< Apply pull-down for PE11 */
13255 …_PD12 PWR_PDCRE_PD12_Msk /*!< Apply pull-down for PE12 */
13258 …_PD13 PWR_PDCRE_PD13_Msk /*!< Apply pull-down for PE13 */
13261 …_PD14 PWR_PDCRE_PD14_Msk /*!< Apply pull-down for PE14 */
13264 …_PD15 PWR_PDCRE_PD15_Msk /*!< Apply pull-down for PE15 */
13270 …RG_PU2 PWR_PUCRG_PU2_Msk /*!< Apply pull-up for PG2 */
13273 …RG_PU3 PWR_PUCRG_PU3_Msk /*!< Apply pull-up for PG3 */
13276 …RG_PU4 PWR_PUCRG_PU4_Msk /*!< Apply pull-up for PG4 */
13279 …RG_PU5 PWR_PUCRG_PU5_Msk /*!< Apply pull-up for PG5 */
13282 …RG_PU6 PWR_PUCRG_PU6_Msk /*!< Apply pull-up for PG6 */
13285 …RG_PU7 PWR_PUCRG_PU7_Msk /*!< Apply pull-up for PG7 */
13288 …RG_PU8 PWR_PUCRG_PU8_Msk /*!< Apply pull-up for PG8 */
13291 …RG_PU9 PWR_PUCRG_PU9_Msk /*!< Apply pull-up for PG9 */
13294 …RG_PU10 PWR_PUCRG_PU10_Msk /*!< Apply pull-up for PG10 */
13297 …RG_PU11 PWR_PUCRG_PU11_Msk /*!< Apply pull-up for PG11 */
13300 …RG_PU12 PWR_PUCRG_PU12_Msk /*!< Apply pull-up for PG12 */
13303 …RG_PU13 PWR_PUCRG_PU13_Msk /*!< Apply pull-up for PG13 */
13306 …RG_PU14 PWR_PUCRG_PU14_Msk /*!< Apply pull-up for PG14 */
13309 …RG_PU15 PWR_PUCRG_PU15_Msk /*!< Apply pull-up for PG15 */
13314 …_PD2 PWR_PDCRG_PD2_Msk /*!< Apply pull-down for PG2 */
13317 …_PD3 PWR_PDCRG_PD3_Msk /*!< Apply pull-down for PG3 */
13320 …_PD4 PWR_PDCRG_PD4_Msk /*!< Apply pull-down for PG4 */
13323 …_PD5 PWR_PDCRG_PD5_Msk /*!< Apply pull-down for PG5 */
13326 …_PD6 PWR_PDCRG_PD6_Msk /*!< Apply pull-down for PG6 */
13329 …_PD7 PWR_PDCRG_PD7_Msk /*!< Apply pull-down for PG7 */
13332 …_PD8 PWR_PDCRG_PD8_Msk /*!< Apply pull-down for PG8 */
13335 …_PD9 PWR_PDCRG_PD9_Msk /*!< Apply pull-down for PG9 */
13338 …_PD10 PWR_PDCRG_PD10_Msk /*!< Apply pull-down for PG10 */
13341 …_PD11 PWR_PDCRG_PD11_Msk /*!< Apply pull-down for PG11 */
13344 …_PD12 PWR_PDCRG_PD12_Msk /*!< Apply pull-down for PG12 */
13347 …_PD13 PWR_PDCRG_PD13_Msk /*!< Apply pull-down for PG13 */
13350 …_PD14 PWR_PDCRG_PD14_Msk /*!< Apply pull-down for PG14 */
13353 …_PD15 PWR_PDCRG_PD15_Msk /*!< Apply pull-down for PG15 */
13358 …RH_PU0 PWR_PUCRH_PU0_Msk /*!< Apply pull-up for PH0 */
13361 …RH_PU1 PWR_PUCRH_PU1_Msk /*!< Apply pull-up for PH1 */
13364 …RH_PU3 PWR_PUCRH_PU3_Msk /*!< Apply pull-up for PH3 */
13369 …_PD0 PWR_PDCRH_PD0_Msk /*!< Apply pull-down for PH0 */
13372 …_PD1 PWR_PDCRH_PD1_Msk /*!< Apply pull-down for PH1 */
13375 …_PD3 PWR_PDCRH_PD3_Msk /*!< Apply pull-down for PH3 */
13676 …PLLFAST_Msk /*!< Internal Multi Speed Oscillator (MSI) PLL Fast Mode Selection */
15106 … RCC_CCIPR1_LPTIM2SEL_Msk /*!< LPTIM2SEL[1:0]: bits (Low-power Timer 2 Kernel …
15249 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk /*!< Low-speed …
15252 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk /*!< Low-speed …
15261 #define RCC_BDCR_LSIPREDIV RCC_BDCR_LSIPREDIV_Msk /*!< Low-speed …
15301 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-power …
15350 #define RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk /*!< RCC Non-Se…
15354 /* Real-Time Clock (RTC) */
15585 …_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
17674 #define SYSCFG_CFGR1_PB6_FMP SYSCFG_CFGR1_PB6_FMP_Msk /*!< PB6 Fast m…
17677 #define SYSCFG_CFGR1_PB7_FMP SYSCFG_CFGR1_PB7_FMP_Msk /*!< PB7 Fast m…
17680 #define SYSCFG_CFGR1_PB8_FMP SYSCFG_CFGR1_PB8_FMP_Msk /*!< PB8 Fast m…
17683 #define SYSCFG_CFGR1_PB9_FMP SYSCFG_CFGR1_PB9_FMP_Msk /*!< PB9 Fast m…
17687 …ne SYSCFG_FPUIMR_FPU_IE_Msk (0x3FUL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */
17689 …U_IE_0 (0x1UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation In…
17690 … (0x2UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt e…
17691 …U_IE_2 (0x4UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt …
17692 …U_IE_3 (0x8UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt e…
17693 …U_IE_4 (0x10UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Inter…
17694 …U_IE_5 (0x20UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt en…
17702 …OCKNSMPU SYSCFG_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers …
18842 … USB_ISTR_IDN_Msk /*!< EndPoint IDentifier (read-only bit) Mask */
18845 … USB_ISTR_DIR_Msk /*!< DIRection of transaction (read-only bit) Mask */
18851 … USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame (clear-only bit) Mask */
18854 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame (clear-…
18860 #define USB_ISTR_DCON USB_ISTR_DCON_Msk /*!< HOST MODE-Device Conne…
18863 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< SUSPend (clear-only bi…
18866 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< WaKe UP (clear-only bi…
18869 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< ERRor (clear-only bit)…
18872 …OVR USB_ISTR_PMAOVR_Msk /*!< PMA OVeR/underrun (clear-only bit) Mask */
18875 …R USB_ISTR_CTR_Msk /*!< Correct TRansfer (clear-only bit) Mask */
18898 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< status of D- data line…
18978 #define USB_BCDR_DPPU USB_BCDR_DPPU_Msk /*!< DP Pull-up Enable Mask…
18981 #define USB_BCDR_DPPD USB_BCDR_DPPD_Msk /*!< DP Pull-Down Enable Ma…
19178 …T_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
19187 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
19212 …T_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
19232 …DDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detec…
19276 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-…
19279 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
19284 …_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
19298 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-P…
19301 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duple…
19340 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
19389 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud …
19446 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud …
19449 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud …
19618 /* Inter-integrated Circuit Interface (I2C) */
19704 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit add…
19707 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit add…
19736 …A1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
19898 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit rece…
19903 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit tran…
19999 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
20005 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC …
20077 …IDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
20165 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet a…
20168 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet s…
20183 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet a…
20317 … WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to L…
20332 … WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
20822 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
20991 /******************** UART Instances : Half-Duplex mode **********************/
21011 /******************** UART Instances : Wake-up from Stop mode **********************/