627   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
642   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
654   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
657   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
680   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
811   uint32_t tmpcr2;  in OC1Config()  local
826   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
857     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
860     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
864   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
890   uint32_t tmpcr2;  in OC2Config()  local
905   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
936     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
939     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
943   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
969   uint32_t tmpcr2;  in OC3Config()  local
984   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
1015     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
1018     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
1022   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1048   uint32_t tmpcr2;  in OC4Config()  local
1063   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1094     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1097     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);  in OC4Config()
1101   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()