550   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
556   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
583   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
639   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
648   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
689   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
820   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
823   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
873   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
899   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
902   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
952   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
978   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
981   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1031   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1057   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1060   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1110   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1137   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1140   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1171   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1198   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1201   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1231   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1254   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1262   MODIFY_REG(TIMx->CCER,  in IC1Config()
1287   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1295   MODIFY_REG(TIMx->CCER,  in IC2Config()
1320   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1328   MODIFY_REG(TIMx->CCER,  in IC3Config()
1353   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1361   MODIFY_REG(TIMx->CCER,  in IC4Config()