367                                           FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
373   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));  in FMC_NORSRAM_Timing_Init()
374   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));  in FMC_NORSRAM_Timing_Init()
375   assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));  in FMC_NORSRAM_Timing_Init()
376   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));  in FMC_NORSRAM_Timing_Init()
377   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));  in FMC_NORSRAM_Timing_Init()
378   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));  in FMC_NORSRAM_Timing_Init()
379   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));  in FMC_NORSRAM_Timing_Init()
380   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));  in FMC_NORSRAM_Timing_Init()
385     (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |  in FMC_NORSRAM_Timing_Init()
386     (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |  in FMC_NORSRAM_Timing_Init()
387     (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |  in FMC_NORSRAM_Timing_Init()
388     (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) |  in FMC_NORSRAM_Timing_Init()
389     (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |  in FMC_NORSRAM_Timing_Init()
390     ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |  in FMC_NORSRAM_Timing_Init()
391     ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |  in FMC_NORSRAM_Timing_Init()
392     Timing->AccessMode;  in FMC_NORSRAM_Timing_Init()
398     tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);  in FMC_NORSRAM_Timing_Init()
418                                                    FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
429     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));  in FMC_NORSRAM_Extended_Timing_Init()
430     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));  in FMC_NORSRAM_Extended_Timing_Init()
431     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));  in FMC_NORSRAM_Extended_Timing_Init()
432     assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));  in FMC_NORSRAM_Extended_Timing_Init()
433     assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));  in FMC_NORSRAM_Extended_Timing_Init()
434     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));  in FMC_NORSRAM_Extended_Timing_Init()
438 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
439 …                                      ((Timing->AddressHoldTime)        << FMC_BWTRx_ADDHLD_Pos)  |  in FMC_NORSRAM_Extended_Timing_Init()
440 …                                      ((Timing->DataSetupTime)          << FMC_BWTRx_DATAST_Pos)  |  in FMC_NORSRAM_Extended_Timing_Init()
441 …                                      ((Timing->DataHoldTime)           << FMC_BWTRx_DATAHLD_Pos) |  in FMC_NORSRAM_Extended_Timing_Init()
442 …                                      Timing->AccessMode                                          |  in FMC_NORSRAM_Extended_Timing_Init()
443 …                                     ((Timing->BusTurnAroundDuration)  << FMC_BWTRx_BUSTURN_Pos)));  in FMC_NORSRAM_Extended_Timing_Init()
600 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
604   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));  in FMC_NAND_CommonSpace_Timing_Init()
605   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));  in FMC_NAND_CommonSpace_Timing_Init()
606   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));  in FMC_NAND_CommonSpace_Timing_Init()
607   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));  in FMC_NAND_CommonSpace_Timing_Init()
614   Device->PMEM =(Timing->SetupTime  |  in FMC_NAND_CommonSpace_Timing_Init()
615     ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |  in FMC_NAND_CommonSpace_Timing_Init()
616     ((Timing->HoldSetupTime )<< FMC_PMEM_MEMHOLD_Pos) |  in FMC_NAND_CommonSpace_Timing_Init()
617     ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos));  in FMC_NAND_CommonSpace_Timing_Init()
631 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
635   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));  in FMC_NAND_AttributeSpace_Timing_Init()
636   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));  in FMC_NAND_AttributeSpace_Timing_Init()
637   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));  in FMC_NAND_AttributeSpace_Timing_Init()
638   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));  in FMC_NAND_AttributeSpace_Timing_Init()
645   Device->PATT =(Timing->SetupTime |  in FMC_NAND_AttributeSpace_Timing_Init()
646       ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |  in FMC_NAND_AttributeSpace_Timing_Init()
647       ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |  in FMC_NAND_AttributeSpace_Timing_Init()
648       ((Timing->HiZSetupTime)  << FMC_PATT_ATTHIZ_Pos));  in FMC_NAND_AttributeSpace_Timing_Init()