Lines Matching refs:hxspi
315 static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, F…
317 static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pC…
353 HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Init() argument
359 if (hxspi == NULL) in HAL_XSPI_Init()
367 assert_param(IS_XSPI_MEMORY_MODE(hxspi->Init.MemoryMode)); in HAL_XSPI_Init()
368 assert_param(IS_XSPI_MEMORY_TYPE(hxspi->Init.MemoryType)); in HAL_XSPI_Init()
369 assert_param(IS_XSPI_MEMORY_SIZE(hxspi->Init.MemorySize)); in HAL_XSPI_Init()
370 assert_param(IS_XSPI_CS_HIGH_TIME_CYCLE(hxspi->Init.ChipSelectHighTimeCycle)); in HAL_XSPI_Init()
371 assert_param(IS_XSPI_FREE_RUN_CLK(hxspi->Init.FreeRunningClock)); in HAL_XSPI_Init()
372 assert_param(IS_XSPI_CLOCK_MODE(hxspi->Init.ClockMode)); in HAL_XSPI_Init()
373 assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize)); in HAL_XSPI_Init()
374 assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler)); in HAL_XSPI_Init()
375 assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting)); in HAL_XSPI_Init()
376 assert_param(IS_XSPI_DHQC(hxspi->Init.DelayHoldQuarterCycle)); in HAL_XSPI_Init()
377 assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); in HAL_XSPI_Init()
378 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
380 assert_param(IS_OCTOSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); in HAL_XSPI_Init()
383 if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
385 assert_param(IS_HSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); in HAL_XSPI_Init()
388 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
390 assert_param(IS_XSPI_DLYB_BYPASS(hxspi->Init.DelayBlockBypass)); in HAL_XSPI_Init()
392 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
394 assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran)); in HAL_XSPI_Init()
397 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Init()
400 if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_Init()
404 hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; in HAL_XSPI_Init()
405 hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; in HAL_XSPI_Init()
406 hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; in HAL_XSPI_Init()
407 hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; in HAL_XSPI_Init()
408 hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; in HAL_XSPI_Init()
409 hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; in HAL_XSPI_Init()
410 hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; in HAL_XSPI_Init()
411 hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; in HAL_XSPI_Init()
412 hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; in HAL_XSPI_Init()
413 hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; in HAL_XSPI_Init()
415 if (hxspi->MspInitCallback == NULL) in HAL_XSPI_Init()
417 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_Init()
421 hxspi->MspInitCallback(hxspi); in HAL_XSPI_Init()
424 HAL_XSPI_MspInit(hxspi); in HAL_XSPI_Init()
428 (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); in HAL_XSPI_Init()
431 MODIFY_REG(hxspi->Instance->DCR1, in HAL_XSPI_Init()
433 (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) | in HAL_XSPI_Init()
434 … ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); in HAL_XSPI_Init()
437 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
439 MODIFY_REG(hxspi->Instance->DCR1, OCTOSPI_DCR1_DLYBYP, hxspi->Init.DelayBlockBypass); in HAL_XSPI_Init()
443 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize); in HAL_XSPI_Init()
446 …MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_… in HAL_XSPI_Init()
449 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
451 MODIFY_REG(hxspi->Instance->DCR3, OCTOSPI_DCR3_MAXTRAN, \ in HAL_XSPI_Init()
452 (hxspi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos)); in HAL_XSPI_Init()
456 hxspi->Instance->DCR4 = hxspi->Init.Refresh; in HAL_XSPI_Init()
459 …MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_F… in HAL_XSPI_Init()
462 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Init()
467 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, in HAL_XSPI_Init()
468 ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); in HAL_XSPI_Init()
471 if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
475 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Init()
483 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_DMM, hxspi->Init.MemoryMode); in HAL_XSPI_Init()
486 MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC), in HAL_XSPI_Init()
487 (hxspi->Init.SampleShifting | hxspi->Init.DelayHoldQuarterCycle)); in HAL_XSPI_Init()
490 HAL_XSPI_ENABLE(hxspi); in HAL_XSPI_Init()
493 if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE) in HAL_XSPI_Init()
495 SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_Init()
499 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Init()
501 hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT; in HAL_XSPI_Init()
505 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Init()
518 __weak void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_MspInit() argument
521 UNUSED(hxspi); in HAL_XSPI_MspInit()
533 HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_DeInit() argument
538 if (hxspi == NULL) in HAL_XSPI_DeInit()
546 HAL_XSPI_DISABLE(hxspi); in HAL_XSPI_DeInit()
549 CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DeInit()
552 if (hxspi->MspDeInitCallback == NULL) in HAL_XSPI_DeInit()
554 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_DeInit()
558 hxspi->MspDeInitCallback(hxspi); in HAL_XSPI_DeInit()
561 HAL_XSPI_MspDeInit(hxspi); in HAL_XSPI_DeInit()
565 hxspi->State = HAL_XSPI_STATE_RESET; in HAL_XSPI_DeInit()
576 __weak void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_MspDeInit() argument
579 UNUSED(hxspi); in HAL_XSPI_MspDeInit()
616 void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_IRQHandler() argument
618 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_IRQHandler()
619 uint32_t flag = hxspi->Instance->SR; in HAL_XSPI_IRQHandler()
620 uint32_t itsource = hxspi->Instance->CR; in HAL_XSPI_IRQHandler()
621 uint32_t currentstate = hxspi->State; in HAL_XSPI_IRQHandler()
629 *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; in HAL_XSPI_IRQHandler()
630 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
631 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
636 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_IRQHandler()
637 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
638 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
645 if (hxspi->XferCount == 0U) in HAL_XSPI_IRQHandler()
649 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_FT); in HAL_XSPI_IRQHandler()
654 hxspi->FifoThresholdCallback(hxspi); in HAL_XSPI_IRQHandler()
656 HAL_XSPI_FifoThresholdCallback(hxspi); in HAL_XSPI_IRQHandler()
664 if ((hxspi->XferCount > 0U) && ((flag & XSPI_SR_FLEVEL) != 0U)) in HAL_XSPI_IRQHandler()
667 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_IRQHandler()
668 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
669 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
671 else if (hxspi->XferCount == 0U) in HAL_XSPI_IRQHandler()
674 hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; in HAL_XSPI_IRQHandler()
677 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
679 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
683 hxspi->RxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
685 HAL_XSPI_RxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
696 hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; in HAL_XSPI_IRQHandler()
699 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
701 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
707 hxspi->TxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
709 HAL_XSPI_TxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
716 hxspi->CmdCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
718 HAL_XSPI_CmdCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
723 if (hxspi->ErrorCode == HAL_XSPI_ERROR_NONE) in HAL_XSPI_IRQHandler()
728 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
730 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
738 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
740 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
754 hxspi->Instance->FCR = HAL_XSPI_FLAG_SM; in HAL_XSPI_IRQHandler()
757 if ((hxspi->Instance->CR & XSPI_CR_APMS) != 0U) in HAL_XSPI_IRQHandler()
760 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
762 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
767 hxspi->StatusMatchCallback(hxspi); in HAL_XSPI_IRQHandler()
769 HAL_XSPI_StatusMatchCallback(hxspi); in HAL_XSPI_IRQHandler()
776 hxspi->Instance->FCR = HAL_XSPI_FLAG_TE; in HAL_XSPI_IRQHandler()
779 …HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HA… in HAL_XSPI_IRQHandler()
782 hxspi->ErrorCode = HAL_XSPI_ERROR_TRANSFER; in HAL_XSPI_IRQHandler()
785 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_IRQHandler()
788 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_IRQHandler()
791 hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_IRQHandler()
792 if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) in HAL_XSPI_IRQHandler()
794 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
798 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
800 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
805 hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_IRQHandler()
806 if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) in HAL_XSPI_IRQHandler()
808 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
812 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
814 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
820 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
824 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
826 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
834 hxspi->Instance->FCR = HAL_XSPI_FLAG_TO; in HAL_XSPI_IRQHandler()
838 hxspi->TimeOutCallback(hxspi); in HAL_XSPI_IRQHandler()
840 HAL_XSPI_TimeOutCallback(hxspi); in HAL_XSPI_IRQHandler()
856 HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, u… in HAL_XSPI_Command() argument
864 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in HAL_XSPI_Command()
866 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command()
871 else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command()
878 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Command()
904 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command()
909 else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command()
911 assert_param(IS_HSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); in HAL_XSPI_Command()
916 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Command()
934 state = hxspi->State; in HAL_XSPI_Command()
935 …if (((state == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERB… in HAL_XSPI_Command()
943 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_Command()
948 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Command()
951 status = XSPI_ConfigCmd(hxspi, pCmd); in HAL_XSPI_Command()
959 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Command()
961 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Command()
968 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
972 if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG) in HAL_XSPI_Command()
974 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
978 hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG; in HAL_XSPI_Command()
983 if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG) in HAL_XSPI_Command()
985 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
989 hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG; in HAL_XSPI_Command()
1007 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Command()
1020 HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd) in HAL_XSPI_Command_IT() argument
1028 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command_IT()
1030 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in HAL_XSPI_Command_IT()
1036 else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command_IT()
1038 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in HAL_XSPI_Command_IT()
1046 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Command_IT()
1071 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command_IT()
1076 else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Command_IT()
1078 assert_param(IS_HSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); in HAL_XSPI_Command_IT()
1083 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Command_IT()
1098 …if ((hxspi->State == HAL_XSPI_STATE_READY) && (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_… in HAL_XSPI_Command_IT()
1099 … (pCmd->DataMode == HAL_XSPI_DATA_NONE) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) in HAL_XSPI_Command_IT()
1102 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Command_IT()
1107 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Command_IT()
1110 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Command_IT()
1113 status = XSPI_ConfigCmd(hxspi, pCmd); in HAL_XSPI_Command_IT()
1118 hxspi->State = HAL_XSPI_STATE_BUSY_CMD; in HAL_XSPI_Command_IT()
1121 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_TE); in HAL_XSPI_Command_IT()
1128 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Command_IT()
1141 HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pC… in HAL_XSPI_HyperbusCfg() argument
1155 state = hxspi->State; in HAL_XSPI_HyperbusCfg()
1159 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_HyperbusCfg()
1164 WRITE_REG(hxspi->Instance->HLCR, ((pCfg->RWRecoveryTimeCycle << XSPI_HLCR_TRWR_Pos) | in HAL_XSPI_HyperbusCfg()
1169 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_HyperbusCfg()
1179 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_HyperbusCfg()
1192 HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pC… in HAL_XSPI_HyperbusCmd() argument
1204 if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_HyperbusCmd()
1206 assert_param(IS_HSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); in HAL_XSPI_HyperbusCmd()
1215 …if ((hxspi->State == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS… in HAL_XSPI_HyperbusCmd()
1218 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_HyperbusCmd()
1223 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); in HAL_XSPI_HyperbusCmd()
1226 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP_0, pCmd->AddressSpace); in HAL_XSPI_HyperbusCmd()
1231 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_HyperbusCmd()
1234 WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | XSPI_CCR_DMODE_2 | in HAL_XSPI_HyperbusCmd()
1236 WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | XSPI_WCCR_DMODE_2 | in HAL_XSPI_HyperbusCmd()
1240 else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_HyperbusCmd()
1243 WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | pCmd->DataMode | in HAL_XSPI_HyperbusCmd()
1245 WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | pCmd->DataMode | in HAL_XSPI_HyperbusCmd()
1255 WRITE_REG(hxspi->Instance->DLR, (pCmd->DataLength - 1U)); in HAL_XSPI_HyperbusCmd()
1258 WRITE_REG(hxspi->Instance->AR, pCmd->Address); in HAL_XSPI_HyperbusCmd()
1261 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_HyperbusCmd()
1271 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_HyperbusCmd()
1285 HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeo… in HAL_XSPI_Transmit() argument
1289 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_Transmit()
1295 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit()
1300 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit()
1303 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Transmit()
1304 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit()
1305 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit()
1308 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit()
1313 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_XSPI_Transmit()
1320 *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; in HAL_XSPI_Transmit()
1321 hxspi->pBuffPtr++; in HAL_XSPI_Transmit()
1322 hxspi->XferCount--; in HAL_XSPI_Transmit()
1323 } while (hxspi->XferCount > 0U); in HAL_XSPI_Transmit()
1328 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Transmit()
1333 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit()
1335 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit()
1342 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit()
1357 HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeou… in HAL_XSPI_Receive() argument
1361 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_Receive()
1362 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive()
1363 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive()
1369 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive()
1374 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive()
1377 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Receive()
1378 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive()
1379 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive()
1382 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive()
1385 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive()
1387 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive()
1391 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive()
1393 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive()
1397 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive()
1404 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, ticksta… in HAL_XSPI_Receive()
1411 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_Receive()
1412 hxspi->pBuffPtr++; in HAL_XSPI_Receive()
1413 hxspi->XferCount--; in HAL_XSPI_Receive()
1414 } while (hxspi->XferCount > 0U); in HAL_XSPI_Receive()
1419 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Receive()
1424 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive()
1426 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive()
1433 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive()
1447 HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) in HAL_XSPI_Transmit_IT() argument
1455 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_IT()
1460 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit_IT()
1463 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Transmit_IT()
1464 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit_IT()
1465 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit_IT()
1468 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit_IT()
1471 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit_IT()
1474 hxspi->State = HAL_XSPI_STATE_BUSY_TX; in HAL_XSPI_Transmit_IT()
1477 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_Transmit_IT()
1482 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit_IT()
1496 HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) in HAL_XSPI_Receive_IT() argument
1499 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive_IT()
1500 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive_IT()
1506 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_IT()
1511 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive_IT()
1514 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Receive_IT()
1515 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive_IT()
1516 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive_IT()
1519 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive_IT()
1522 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive_IT()
1525 hxspi->State = HAL_XSPI_STATE_BUSY_RX; in HAL_XSPI_Receive_IT()
1528 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_Receive_IT()
1531 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive_IT()
1533 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_IT()
1537 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive_IT()
1539 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_IT()
1543 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive_IT()
1550 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive_IT()
1568 HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) in HAL_XSPI_Transmit_DMA() argument
1571 uint32_t data_size = hxspi->Instance->DLR + 1U; in HAL_XSPI_Transmit_DMA()
1579 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1584 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit_DMA()
1586 if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Transmit_DMA()
1588 p_queue = hxspi->hdmatx->LinkedListQueue; in HAL_XSPI_Transmit_DMA()
1596 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1604 data_width = hxspi->hdmatx->Init.DestDataWidth; in HAL_XSPI_Transmit_DMA()
1609 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1613 if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) in HAL_XSPI_Transmit_DMA()
1617 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1622 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1627 if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) in HAL_XSPI_Transmit_DMA()
1631 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1636 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1646 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit_DMA()
1647 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit_DMA()
1650 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit_DMA()
1653 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit_DMA()
1656 hxspi->State = HAL_XSPI_STATE_BUSY_TX; in HAL_XSPI_Transmit_DMA()
1659 hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt; in HAL_XSPI_Transmit_DMA()
1662 hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt; in HAL_XSPI_Transmit_DMA()
1665 hxspi->hdmatx->XferErrorCallback = XSPI_DMAError; in HAL_XSPI_Transmit_DMA()
1668 hxspi->hdmatx->XferAbortCallback = NULL; in HAL_XSPI_Transmit_DMA()
1671 if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Transmit_DMA()
1673 if (hxspi->hdmatx->LinkedListQueue != NULL) in HAL_XSPI_Transmit_DMA()
1681 p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; in HAL_XSPI_Transmit_DMA()
1685 p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; in HAL_XSPI_Transmit_DMA()
1687 status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx); in HAL_XSPI_Transmit_DMA()
1692 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1694 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit_DMA()
1702 if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && in HAL_XSPI_Transmit_DMA()
1703 …(hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_F… in HAL_XSPI_Transmit_DMA()
1705 …status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->X… in HAL_XSPI_Transmit_DMA()
1710 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1717 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); in HAL_XSPI_Transmit_DMA()
1720 SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Transmit_DMA()
1725 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1726 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit_DMA()
1733 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit_DMA()
1751 HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) in HAL_XSPI_Receive_DMA() argument
1754 uint32_t data_size = hxspi->Instance->DLR + 1U; in HAL_XSPI_Receive_DMA()
1755 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive_DMA()
1756 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive_DMA()
1764 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1769 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive_DMA()
1771 if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Receive_DMA()
1773 p_queue = hxspi->hdmarx->LinkedListQueue; in HAL_XSPI_Receive_DMA()
1781 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1789 data_width = hxspi->hdmarx->Init.DestDataWidth; in HAL_XSPI_Receive_DMA()
1795 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1799 if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) in HAL_XSPI_Receive_DMA()
1803 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1808 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1813 if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) in HAL_XSPI_Receive_DMA()
1817 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1822 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1832 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive_DMA()
1833 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive_DMA()
1836 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive_DMA()
1839 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive_DMA()
1842 hxspi->State = HAL_XSPI_STATE_BUSY_RX; in HAL_XSPI_Receive_DMA()
1845 hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt; in HAL_XSPI_Receive_DMA()
1848 hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt; in HAL_XSPI_Receive_DMA()
1851 hxspi->hdmarx->XferErrorCallback = XSPI_DMAError; in HAL_XSPI_Receive_DMA()
1854 hxspi->hdmarx->XferAbortCallback = NULL; in HAL_XSPI_Receive_DMA()
1857 if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Receive_DMA()
1859 if (hxspi->hdmarx->LinkedListQueue != NULL) in HAL_XSPI_Receive_DMA()
1867 p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; in HAL_XSPI_Receive_DMA()
1869 p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; in HAL_XSPI_Receive_DMA()
1873 status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx); in HAL_XSPI_Receive_DMA()
1878 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1880 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive_DMA()
1888 …if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_… in HAL_XSPI_Receive_DMA()
1889 && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED)) in HAL_XSPI_Receive_DMA()
1891 …status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->X… in HAL_XSPI_Receive_DMA()
1896 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1903 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); in HAL_XSPI_Receive_DMA()
1906 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive_DMA()
1908 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_DMA()
1912 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive_DMA()
1914 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_DMA()
1918 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive_DMA()
1923 SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Receive_DMA()
1928 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1929 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive_DMA()
1936 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive_DMA()
1951 HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pC… in HAL_XSPI_AutoPolling() argument
1956 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_AutoPolling()
1957 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_AutoPolling()
1959 uint32_t dlr_reg = hxspi->Instance->DLR; in HAL_XSPI_AutoPolling()
1969 …if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_EN… in HAL_XSPI_AutoPolling()
1972 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_AutoPolling()
1977 WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); in HAL_XSPI_AutoPolling()
1978 WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); in HAL_XSPI_AutoPolling()
1979 WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); in HAL_XSPI_AutoPolling()
1980 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), in HAL_XSPI_AutoPolling()
1984 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_AutoPolling()
1986 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling()
1990 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_AutoPolling()
1992 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling()
1996 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_AutoPolling()
2001 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_XSPI_AutoPolling()
2006 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM); in HAL_XSPI_AutoPolling()
2008 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_AutoPolling()
2019 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_AutoPolling()
2032 HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const… in HAL_XSPI_AutoPolling_IT() argument
2036 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_AutoPolling_IT()
2037 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_AutoPolling_IT()
2039 uint32_t dlr_reg = hxspi->Instance->DLR; in HAL_XSPI_AutoPolling_IT()
2049 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_AutoPolling_IT()
2052 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_AutoPolling_IT()
2057 WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); in HAL_XSPI_AutoPolling_IT()
2058 WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); in HAL_XSPI_AutoPolling_IT()
2059 WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); in HAL_XSPI_AutoPolling_IT()
2060 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), in HAL_XSPI_AutoPolling_IT()
2064 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_SM); in HAL_XSPI_AutoPolling_IT()
2066 hxspi->State = HAL_XSPI_STATE_BUSY_AUTO_POLLING; in HAL_XSPI_AutoPolling_IT()
2069 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); in HAL_XSPI_AutoPolling_IT()
2072 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_AutoPolling_IT()
2074 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling_IT()
2078 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_AutoPolling_IT()
2080 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling_IT()
2084 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_AutoPolling_IT()
2092 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_AutoPolling_IT()
2105 HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const … in HAL_XSPI_MemoryMapped() argument
2114 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_MemoryMapped()
2117 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_MemoryMapped()
2121 hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; in HAL_XSPI_MemoryMapped()
2128 WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock); in HAL_XSPI_MemoryMapped()
2131 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO); in HAL_XSPI_MemoryMapped()
2134 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO); in HAL_XSPI_MemoryMapped()
2138 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), in HAL_XSPI_MemoryMapped()
2145 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_MemoryMapped()
2156 __weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_ErrorCallback() argument
2159 UNUSED(hxspi); in HAL_XSPI_ErrorCallback()
2171 __weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_AbortCpltCallback() argument
2174 UNUSED(hxspi); in HAL_XSPI_AbortCpltCallback()
2186 __weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_FifoThresholdCallback() argument
2189 UNUSED(hxspi); in HAL_XSPI_FifoThresholdCallback()
2201 __weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_CmdCpltCallback() argument
2204 UNUSED(hxspi); in HAL_XSPI_CmdCpltCallback()
2216 __weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_RxCpltCallback() argument
2219 UNUSED(hxspi); in HAL_XSPI_RxCpltCallback()
2231 __weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TxCpltCallback() argument
2234 UNUSED(hxspi); in HAL_XSPI_TxCpltCallback()
2246 __weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_RxHalfCpltCallback() argument
2249 UNUSED(hxspi); in HAL_XSPI_RxHalfCpltCallback()
2261 __weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TxHalfCpltCallback() argument
2264 UNUSED(hxspi); in HAL_XSPI_TxHalfCpltCallback()
2276 __weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_StatusMatchCallback() argument
2279 UNUSED(hxspi); in HAL_XSPI_StatusMatchCallback()
2291 __weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TimeOutCallback() argument
2294 UNUSED(hxspi); in HAL_XSPI_TimeOutCallback()
2323 HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef C… in HAL_XSPI_RegisterCallback() argument
2331 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2335 if (hxspi->State == HAL_XSPI_STATE_READY) in HAL_XSPI_RegisterCallback()
2340 hxspi->ErrorCallback = pCallback; in HAL_XSPI_RegisterCallback()
2343 hxspi->AbortCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2346 hxspi->FifoThresholdCallback = pCallback; in HAL_XSPI_RegisterCallback()
2349 hxspi->CmdCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2352 hxspi->RxCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2355 hxspi->TxCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2358 hxspi->RxHalfCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2361 hxspi->TxHalfCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2364 hxspi->StatusMatchCallback = pCallback; in HAL_XSPI_RegisterCallback()
2367 hxspi->TimeOutCallback = pCallback; in HAL_XSPI_RegisterCallback()
2370 hxspi->MspInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2373 hxspi->MspDeInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2377 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2383 else if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_RegisterCallback()
2388 hxspi->MspInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2391 hxspi->MspDeInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2395 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2404 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2432 HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef… in HAL_XSPI_UnRegisterCallback() argument
2436 if (hxspi->State == HAL_XSPI_STATE_READY) in HAL_XSPI_UnRegisterCallback()
2441 hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; in HAL_XSPI_UnRegisterCallback()
2444 hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; in HAL_XSPI_UnRegisterCallback()
2447 hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; in HAL_XSPI_UnRegisterCallback()
2450 hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; in HAL_XSPI_UnRegisterCallback()
2453 hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; in HAL_XSPI_UnRegisterCallback()
2456 hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; in HAL_XSPI_UnRegisterCallback()
2459 hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; in HAL_XSPI_UnRegisterCallback()
2462 hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; in HAL_XSPI_UnRegisterCallback()
2465 hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; in HAL_XSPI_UnRegisterCallback()
2468 hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; in HAL_XSPI_UnRegisterCallback()
2471 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_UnRegisterCallback()
2474 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_UnRegisterCallback()
2478 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2484 else if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_UnRegisterCallback()
2489 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_UnRegisterCallback()
2492 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_UnRegisterCallback()
2496 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2505 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2542 HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Abort() argument
2548 if (hxspi->State != HAL_XSPI_STATE_RESET) in HAL_XSPI_Abort()
2551 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_Abort()
2554 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Abort()
2557 status = HAL_DMA_Abort(hxspi->hdmatx); in HAL_XSPI_Abort()
2560 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Abort()
2564 status = HAL_DMA_Abort(hxspi->hdmarx); in HAL_XSPI_Abort()
2567 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Abort()
2571 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in HAL_XSPI_Abort()
2574 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in HAL_XSPI_Abort()
2577 … status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout); in HAL_XSPI_Abort()
2582 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Abort()
2585 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Abort()
2590 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort()
2592 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort()
2599 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort()
2601 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort()
2607 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Abort()
2618 HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Abort_IT() argument
2623 if (hxspi->State != HAL_XSPI_STATE_RESET) in HAL_XSPI_Abort_IT()
2626 …HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HA… in HAL_XSPI_Abort_IT()
2628 hxspi->State = HAL_XSPI_STATE_ABORT; in HAL_XSPI_Abort_IT()
2631 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_Abort_IT()
2634 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Abort_IT()
2637 hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_Abort_IT()
2638 if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) in HAL_XSPI_Abort_IT()
2640 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2644 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2646 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2651 hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_Abort_IT()
2652 if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) in HAL_XSPI_Abort_IT()
2654 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2658 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2660 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2666 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in HAL_XSPI_Abort_IT()
2669 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Abort_IT()
2672 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in HAL_XSPI_Abort_IT()
2675 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in HAL_XSPI_Abort_IT()
2678 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort_IT()
2683 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort_IT()
2685 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2689 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2691 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2699 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Abort_IT()
2710 HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold) in HAL_XSPI_SetFifoThreshold() argument
2714 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_SetFifoThreshold()
2719 else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_SetFifoThreshold()
2726 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_SetFifoThreshold()
2731 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetFifoThreshold()
2734 hxspi->Init.FifoThresholdByte = Threshold; in HAL_XSPI_SetFifoThreshold()
2737 …MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_F… in HAL_XSPI_SetFifoThreshold()
2743 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetFifoThreshold()
2753 uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetFifoThreshold() argument
2755 return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U); in HAL_XSPI_GetFifoThreshold()
2763 HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type) in HAL_XSPI_SetMemoryType() argument
2770 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetMemoryType()
2773 hxspi->Init.MemoryType = Type; in HAL_XSPI_SetMemoryType()
2776 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP, hxspi->Init.MemoryType); in HAL_XSPI_SetMemoryType()
2781 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetMemoryType()
2792 HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size) in HAL_XSPI_SetDeviceSize() argument
2799 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetDeviceSize()
2802 hxspi->Init.MemorySize = Size; in HAL_XSPI_SetDeviceSize()
2805 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, in HAL_XSPI_SetDeviceSize()
2806 (hxspi->Init.MemorySize << XSPI_DCR1_DEVSIZE_Pos)); in HAL_XSPI_SetDeviceSize()
2811 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetDeviceSize()
2822 HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler) in HAL_XSPI_SetClockPrescaler() argument
2828 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetClockPrescaler()
2831 hxspi->Init.ClockPrescaler = Prescaler; in HAL_XSPI_SetClockPrescaler()
2834 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, in HAL_XSPI_SetClockPrescaler()
2835 ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); in HAL_XSPI_SetClockPrescaler()
2840 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetClockPrescaler()
2851 HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout) in HAL_XSPI_SetTimeout() argument
2853 hxspi->Timeout = Timeout; in HAL_XSPI_SetTimeout()
2862 uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetError() argument
2864 return hxspi->ErrorCode; in HAL_XSPI_GetError()
2872 uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetState() argument
2875 return hxspi->State; in HAL_XSPI_GetState()
2905 HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, u… in HAL_XSPIM_Config() argument
2925 if (hxspi->Instance == OCTOSPI1) in HAL_XSPIM_Config()
2930 else if (hxspi->Instance == OCTOSPI2) in HAL_XSPIM_Config()
2937 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPIM_Config()
3168 HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *con… in HAL_XSPI_DLYB_SetConfig() argument
3173 SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_SetConfig()
3176 hxspi->State = HAL_XSPI_STATE_BUSY_CMD; in HAL_XSPI_DLYB_SetConfig()
3178 if (hxspi->Instance == OCTOSPI1) in HAL_XSPI_DLYB_SetConfig()
3188 else if (hxspi->Instance == OCTOSPI2) in HAL_XSPI_DLYB_SetConfig()
3200 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_DLYB_SetConfig()
3204 (void)HAL_XSPI_Abort(hxspi); in HAL_XSPI_DLYB_SetConfig()
3207 CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_SetConfig()
3218 HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *con… in HAL_XSPI_DLYB_GetConfig() argument
3222 if (hxspi->Instance == OCTOSPI1) in HAL_XSPI_DLYB_GetConfig()
3228 else if (hxspi->Instance == OCTOSPI2) in HAL_XSPI_DLYB_GetConfig()
3236 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_DLYB_GetConfig()
3248 HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef … in HAL_XSPI_DLYB_GetClockPeriod() argument
3253 SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_GetClockPeriod()
3256 hxspi->State = HAL_XSPI_STATE_BUSY_CMD; in HAL_XSPI_DLYB_GetClockPeriod()
3258 if (hxspi->Instance == OCTOSPI1) in HAL_XSPI_DLYB_GetClockPeriod()
3273 else if (hxspi->Instance == OCTOSPI2) in HAL_XSPI_DLYB_GetClockPeriod()
3290 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_DLYB_GetClockPeriod()
3294 (void)HAL_XSPI_Abort(hxspi); in HAL_XSPI_DLYB_GetClockPeriod()
3297 CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_GetClockPeriod()
3329 HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) in HAL_XSPI_GetDelayValue() argument
3334 if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_GetDelayValue()
3342 reg = hxspi->Instance->CALFCR; in HAL_XSPI_GetDelayValue()
3346 reg = hxspi->Instance->CALMR; in HAL_XSPI_GetDelayValue()
3349 reg = hxspi->Instance->CALSOR; in HAL_XSPI_GetDelayValue()
3352 reg = hxspi->Instance->CALSIR; in HAL_XSPI_GetDelayValue()
3356 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_GetDelayValue()
3369 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_GetDelayValue()
3381 HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) in HAL_XSPI_SetDelayValue() argument
3385 if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_SetDelayValue()
3393 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetDelayValue()
3398 MODIFY_REG(hxspi->Instance->CALMR, (HSPI_CALMR_COARSE | HSPI_CALMR_FINE), in HAL_XSPI_SetDelayValue()
3402 MODIFY_REG(hxspi->Instance->CALSOR, (HSPI_CALSOR_COARSE | HSPI_CALSOR_FINE), in HAL_XSPI_SetDelayValue()
3406 MODIFY_REG(hxspi->Instance->CALSIR, (HSPI_CALSIR_COARSE | HSPI_CALSIR_FINE), in HAL_XSPI_SetDelayValue()
3411 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_SetDelayValue()
3418 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetDelayValue()
3424 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_SetDelayValue()
3445 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMACplt() local
3446 hxspi->XferCount = 0; in XSPI_DMACplt()
3449 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in XSPI_DMACplt()
3452 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in XSPI_DMACplt()
3462 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAHalfCplt() local
3463 hxspi->XferCount = (hxspi->XferCount >> 1); in XSPI_DMAHalfCplt()
3465 if (hxspi->State == HAL_XSPI_STATE_BUSY_RX) in XSPI_DMAHalfCplt()
3468 hxspi->RxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3470 HAL_XSPI_RxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3476 hxspi->TxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3478 HAL_XSPI_TxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3490 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAError() local
3491 hxspi->XferCount = 0; in XSPI_DMAError()
3492 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in XSPI_DMAError()
3495 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in XSPI_DMAError()
3498 if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) in XSPI_DMAError()
3501 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in XSPI_DMAError()
3503 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAError()
3507 hxspi->ErrorCallback(hxspi); in XSPI_DMAError()
3509 HAL_XSPI_ErrorCallback(hxspi); in XSPI_DMAError()
3521 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAAbortCplt() local
3522 hxspi->XferCount = 0; in XSPI_DMAAbortCplt()
3525 if (hxspi->State == HAL_XSPI_STATE_ABORT) in XSPI_DMAAbortCplt()
3528 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in XSPI_DMAAbortCplt()
3531 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in XSPI_DMAAbortCplt()
3534 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in XSPI_DMAAbortCplt()
3537 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in XSPI_DMAAbortCplt()
3541 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAAbortCplt()
3545 hxspi->AbortCpltCallback(hxspi); in XSPI_DMAAbortCplt()
3547 HAL_XSPI_AbortCpltCallback(hxspi); in XSPI_DMAAbortCplt()
3554 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAAbortCplt()
3558 hxspi->ErrorCallback(hxspi); in XSPI_DMAAbortCplt()
3560 HAL_XSPI_ErrorCallback(hxspi); in XSPI_DMAAbortCplt()
3574 static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, in XSPI_WaitFlagStateUntilTimeout() argument
3578 while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) in XSPI_WaitFlagStateUntilTimeout()
3585 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_WaitFlagStateUntilTimeout()
3586 hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; in XSPI_WaitFlagStateUntilTimeout()
3601 static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd) in XSPI_ConfigCmd() argument
3610 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); in XSPI_ConfigCmd()
3612 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in XSPI_ConfigCmd()
3614 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in XSPI_ConfigCmd()
3617 MODIFY_REG(hxspi->Instance->CR, OCTOSPI_CR_MSEL, pCmd->IOSelect); in XSPI_ConfigCmd()
3621 else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) in XSPI_ConfigCmd()
3623 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in XSPI_ConfigCmd()
3626 MODIFY_REG(hxspi->Instance->CR, HSPI_CR_MSEL, pCmd->IOSelect); in XSPI_ConfigCmd()
3632 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in XSPI_ConfigCmd()
3638 ccr_reg = &(hxspi->Instance->WCCR); in XSPI_ConfigCmd()
3639 tcr_reg = &(hxspi->Instance->WTCR); in XSPI_ConfigCmd()
3640 ir_reg = &(hxspi->Instance->WIR); in XSPI_ConfigCmd()
3641 abr_reg = &(hxspi->Instance->WABR); in XSPI_ConfigCmd()
3645 ccr_reg = &(hxspi->Instance->WPCCR); in XSPI_ConfigCmd()
3646 tcr_reg = &(hxspi->Instance->WPTCR); in XSPI_ConfigCmd()
3647 ir_reg = &(hxspi->Instance->WPIR); in XSPI_ConfigCmd()
3648 abr_reg = &(hxspi->Instance->WPABR); in XSPI_ConfigCmd()
3652 ccr_reg = &(hxspi->Instance->CCR); in XSPI_ConfigCmd()
3653 tcr_reg = &(hxspi->Instance->TCR); in XSPI_ConfigCmd()
3654 ir_reg = &(hxspi->Instance->IR); in XSPI_ConfigCmd()
3655 abr_reg = &(hxspi->Instance->ABR); in XSPI_ConfigCmd()
3687 hxspi->Instance->DLR = (pCmd->DataLength - 1U); in XSPI_ConfigCmd()
3697 CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); in XSPI_ConfigCmd()
3699 else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) in XSPI_ConfigCmd()
3702 SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); in XSPI_ConfigCmd()
3737 if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && in XSPI_ConfigCmd()
3747 hxspi->Instance->AR = pCmd->Address; in XSPI_ConfigCmd()
3770 if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && in XSPI_ConfigCmd()
3806 hxspi->Instance->AR = pCmd->Address; in XSPI_ConfigCmd()
3812 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in XSPI_ConfigCmd()