351         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_DeInit()
368   hdma2d->Instance->FGPFCCR  =    0U;  in HAL_DMA2D_DeInit()
999     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_EnableCLUT()
1050     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad()
1054     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad()
1108     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad_IT()
1115     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad_IT()
1168     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad()
1172     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad()
1228     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad_IT()
1235     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad_IT()
1261     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Abort()
1319     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Suspend()
1392       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_CLUTLoading_Resume()
1471   layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;  in HAL_DMA2D_PollForTransfer()
1851     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);  in HAL_DMA2D_ConfigLayer()
1916     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_ConfigCLUT()