Lines Matching refs:PWR
34 #if defined (PWR)
496 #define LL_PWR_GPIO_PORTA (&(PWR->PUCRA)) /*!< GPIO port A */
497 #define LL_PWR_GPIO_PORTB (&(PWR->PUCRB)) /*!< GPIO port B */
498 #define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */
499 #define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */
500 #define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */
502 #define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */
504 #define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */
505 #define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */
507 #define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */
510 #define LL_PWR_GPIO_PORTJ (&(PWR->PUCRJ)) /*!< GPIO port J */
591 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
598 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
631 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode); in LL_PWR_SetPowerMode()
647 return (READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
663 MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_SB_FULL_RETENTION, SRAM2PageRetention); in LL_PWR_SetSRAM2SBRetention()
678 return (READ_BIT(PWR->CR1, (PWR_CR1_RRSB1 | PWR_CR1_RRSB2))); in LL_PWR_GetSRAM2SBRetention()
688 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); in LL_PWR_EnableUltraLowPowerMode()
698 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); in LL_PWR_DisableUltraLowPowerMode()
708 return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUltraLowPowerMode()
721 …MODIFY_REG(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION, ((~SRAM1Retention) & LL_PWR_SRAM1_RUN_FULL_R… in LL_PWR_SetSRAM1RunRetention()
733 …return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION))) & LL_PWR_SRAM1_RUN_FULL_RETENTION… in LL_PWR_GetSRAM1RunRetention()
746 …MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION, ((~SRAM2Retention) & LL_PWR_SRAM2_RUN_FULL_R… in LL_PWR_SetSRAM2RunRetention()
758 …return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION… in LL_PWR_GetSRAM2RunRetention()
772 …MODIFY_REG(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION, ((~SRAM3Retention) & LL_PWR_SRAM3_RUN_FULL_R… in LL_PWR_SetSRAM3RunRetention()
784 …return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION… in LL_PWR_GetSRAM3RunRetention()
798 …MODIFY_REG(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION, ((~SRAM4Retention) & LL_PWR_SRAM4_RUN_FULL_R… in LL_PWR_SetSRAM4RunRetention()
810 …return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION… in LL_PWR_GetSRAM4RunRetention()
824 …MODIFY_REG(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION, ((~SRAM5Retention) & LL_PWR_SRAM5_RUN_FULL_R… in LL_PWR_SetSRAM5RunRetention()
836 …return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION))) & LL_PWR_SRAM5_RUN_FULL_RETENTION… in LL_PWR_GetSRAM5RunRetention()
851 …MODIFY_REG(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION, ((~SRAM6Retention) & LL_PWR_SRAM6_RUN_FULL_R… in LL_PWR_SetSRAM6RunRetention()
863 …return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION))) & LL_PWR_SRAM6_RUN_FULL_RETENTION… in LL_PWR_GetSRAM6RunRetention()
875 SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); in LL_PWR_EnableOTGHSPHYLowPowerRetention()
885 CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); in LL_PWR_DisableOTGHSPHYLowPowerRetention()
895 return ((READ_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR) == (PWR_CR1_FORCE_USBPWR)) ? 1UL : 0UL); in LL_PWR_IsEnabledOTGHSPHYLowPowerRetention()
915 …MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1… in LL_PWR_SetSRAM1StopRetention_1_3()
947 …MODIFY_REG(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_… in LL_PWR_SetSRAM1StopRetention_4_12()
966 …return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION… in LL_PWR_GetSRAM1StopRetention_1_3()
997 …return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION))) & LL_PWR_SRAM1_STOP_4_12_RETENTI… in LL_PWR_GetSRAM1StopRetention_4_12()
1014 …MODIFY_REG(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION, ((~SRAM2PageRetention) & LL_PWR_SRAM2_STOP_… in LL_PWR_SetSRAM2StopRetention()
1029 …return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTI… in LL_PWR_GetSRAM2StopRetention()
1059 …MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1… in LL_PWR_SetSRAM3StopRetention_1_8()
1083 …MODIFY_REG(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_… in LL_PWR_SetSRAM3StopRetention_9_13()
1112 …return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION… in LL_PWR_GetSRAM3StopRetention_1_8()
1135 …return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION))) & LL_PWR_SRAM3_STOP_9_13_RETENTI… in LL_PWR_GetSRAM3StopRetention_9_13()
1150 …MODIFY_REG(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION, ((~SRAM4PageRetention) & LL_PWR_SRAM4_STOP_… in LL_PWR_SetSRAM4StopRetention()
1162 …return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTI… in LL_PWR_GetSRAM4StopRetention()
1202 …MODIFY_REG(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION, ((~SRAM5PageRetention) & LL_PWR_SRAM5_STOP_… in LL_PWR_SetSRAM5StopRetention()
1240 …return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION))) & LL_PWR_SRAM5_STOP_FULL_RETENTI… in LL_PWR_GetSRAM5StopRetention()
1271 …MODIFY_REG(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION, ((~SRAM6PageRetention) & LL_PWR_SRAM6_STOP_… in LL_PWR_SetSRAM6StopRetention()
1299 …return ((~(READ_BIT(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION))) & LL_PWR_SRAM6_STOP_FULL_RETENTI… in LL_PWR_GetSRAM6StopRetention()
1313 MODIFY_REG(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION, in LL_PWR_SetICacheRAMStopRetention()
1326 …return ((~(READ_BIT(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION))) & LL_PWR_ICACHERAM_STOP_FULL… in LL_PWR_GetICacheRAMStopRetention()
1339 MODIFY_REG(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION, in LL_PWR_SetDCache1RAMStopRetention()
1352 …return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FU… in LL_PWR_GetDCache1RAMStopRetention()
1366 MODIFY_REG(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION, in LL_PWR_SetDCache2RAMStopRetention()
1379 …return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE2RAM_STOP_FU… in LL_PWR_GetDCache2RAMStopRetention()
1394 MODIFY_REG(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION, in LL_PWR_SetDMA2DRAMStopRetention()
1407 …return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_R… in LL_PWR_GetDMA2DRAMStopRetention()
1421 MODIFY_REG(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION, in LL_PWR_SetPeriphRAMStopRetention()
1434 …return ((~(READ_BIT(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION))) & LL_PWR_PERIPHRAM_STOP_FULL… in LL_PWR_GetPeriphRAMStopRetention()
1448 …MODIFY_REG(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION, ((~PKARAMPageRetention) & LL_PWR_PKARAM_ST… in LL_PWR_SetPKARAMStopRetention()
1460 …return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETEN… in LL_PWR_GetPKARAMStopRetention()
1475 MODIFY_REG(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION, in LL_PWR_SetGraphicPeriphRAMStopRetention()
1488 return ((~(READ_BIT(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION))) & in LL_PWR_GetGraphicPeriphRAMStopRetention()
1504 …MODIFY_REG(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION, ((~DSIRAMPageRetention) & LL_PWR_DSIRAM_ST… in LL_PWR_SetDSIRAMStopRetention()
1516 …return ((~(READ_BIT(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION))) & LL_PWR_DSIRAM_STOP_FULL_RETEN… in LL_PWR_GetDSIRAMStopRetention()
1531 MODIFY_REG(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION, in LL_PWR_SetJPEGRAMStopRetention()
1544 …return ((~(READ_BIT(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION))) & LL_PWR_JPEGRAM_STOP_FULL_RET… in LL_PWR_GetJPEGRAMStopRetention()
1555 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); in LL_PWR_EnableFlashFastWakeUp()
1565 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); in LL_PWR_DisableFlashFastWakeUp()
1576 return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashFastWakeUp()
1586 SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); in LL_PWR_EnableSRAM4FastWakeUp()
1596 CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); in LL_PWR_DisableSRAM4FastWakeUp()
1607 return ((READ_BIT(PWR->CR2, PWR_CR2_SRAM4FWU) == (PWR_CR2_SRAM4FWU)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAM4FastWakeUp()
1620 MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDMode); in LL_PWR_SetSmartRunDomainMode()
1632 return (READ_BIT(PWR->CR2, PWR_CR2_SRDRUN)); in LL_PWR_GetSmartRunDomainMode()
1645 MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply); in LL_PWR_SetRegulatorSupply()
1657 return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL)); in LL_PWR_GetRegulatorSupply()
1667 SET_BIT(PWR->CR3, PWR_CR3_FSTEN); in LL_PWR_EnableFastSoftStart()
1677 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); in LL_PWR_DisableFastSoftStart()
1687 return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledFastSoftStart()
1702 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
1716 return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS)); in LL_PWR_GetRegulVoltageScaling()
1726 SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); in LL_PWR_EnableEPODBooster()
1736 CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); in LL_PWR_DisableEPODBooster()
1746 return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledEPODBooster()
1757 SET_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); in LL_PWR_EnableUSBPowerSupply()
1767 CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); in LL_PWR_DisableUSBPowerSupply()
1777 return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBPWREN) == (PWR_VOSR_USBPWREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBPowerSupply()
1789 SET_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); in LL_PWR_EnableUSBEPODBooster()
1799 CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); in LL_PWR_DisableUSBEPODBooster()
1809 return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN) == (PWR_VOSR_USBBOOSTEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBEPODBooster()
1821 CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); in LL_PWR_EnableVDD11USB()
1831 SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); in LL_PWR_DisableVDD11USB()
1841 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS) == (0U)) ? 1UL : 0UL); in LL_PWR_IsEnabledVDD11USB()
1861 MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel); in LL_PWR_SetPVDLevel()
1879 return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS)); in LL_PWR_GetPVDLevel()
1889 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); in LL_PWR_EnablePVD()
1899 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); in LL_PWR_DisablePVD()
1909 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
1919 SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); in LL_PWR_EnableVddUSB()
1930 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); in LL_PWR_DisableVddUSB()
1941 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSB()
1952 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); in LL_PWR_EnableVddIO2()
1963 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); in LL_PWR_DisableVddIO2()
1974 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO2()
1985 SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV); in LL_PWR_EnableVddA()
1996 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV); in LL_PWR_DisableVddA()
2007 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddA()
2018 SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); in LL_PWR_EnableVddUSBMonitor()
2029 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); in LL_PWR_DisableVddUSBMonitor()
2040 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSBMonitor()
2051 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); in LL_PWR_EnableVddIO2Monitor()
2062 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); in LL_PWR_DisableVddIO2Monitor()
2073 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO2Monitor()
2084 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); in LL_PWR_EnableVddAMonitor1()
2095 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); in LL_PWR_DisableVddAMonitor1()
2106 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddAMonitor1()
2117 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); in LL_PWR_EnableVddAMonitor2()
2128 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); in LL_PWR_DisableVddAMonitor2()
2139 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddAMonitor2()
2159 SET_BIT(PWR->WUCR1, WakeUpPin); in LL_PWR_EnableWakeUpPin()
2178 CLEAR_BIT(PWR->WUCR1, WakeUpPin); in LL_PWR_DisableWakeUpPin()
2197 return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
2216 SET_BIT(PWR->WUCR2, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityLow()
2235 CLEAR_BIT(PWR->WUCR2, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityHigh()
2254 return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL); in LL_PWR_GetWakeUpPinPolarity()
2273 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal0Selection()
2293 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal1Selection()
2313 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal2Selection()
2333 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), in LL_PWR_SetWakeUpPinSignal3Selection()
2352 return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)))); in LL_PWR_GetWakeUpPinSignalSelection()
2367 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in LL_PWR_EnableBkUpRegulator()
2377 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in LL_PWR_DisableBkUpRegulator()
2387 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpRegulator()
2397 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_EnableMonitoring()
2407 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_DisableMonitoring()
2418 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
2428 SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE); in LL_PWR_EnableBatteryCharging()
2438 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE); in LL_PWR_DisableBatteryCharging()
2448 return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
2461 MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
2473 return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS)); in LL_PWR_GetBattChargResistor()
2483 SET_BIT(PWR->DBPR, PWR_DBPR_DBP); in LL_PWR_EnableBkUpAccess()
2493 CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); in LL_PWR_DisableBkUpAccess()
2503 return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
2515 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); in LL_PWR_EnableUCPDStandbyMode()
2527 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); in LL_PWR_DisableUCPDStandbyMode()
2537 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY) == (PWR_UCPDR_UCPD_STDBY)) ? 1UL : 0UL); in LL_PWR_IsEnabledUCPDStandbyMode()
2552 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); in LL_PWR_EnableUCPDDeadBattery()
2567 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); in LL_PWR_DisableUCPDDeadBattery()
2582 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL); in LL_PWR_IsEnabledUCPDDeadBattery()
2593 SET_BIT(PWR->APCR, PWR_APCR_APC); in LL_PWR_EnablePUPDConfig()
2603 CLEAR_BIT(PWR->APCR, PWR_APCR_APC); in LL_PWR_DisablePUPDConfig()
2613 return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDConfig()
2861 return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS)); in LL_PWR_GetRegulCurrentVOS()
2879 return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BOOST()
2891 return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == (PWR_VOSR_USBBOOSTRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_USBBOOST()
2903 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
2913 return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
2923 return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_STOP()
2933 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGULATOR()
2943 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
2954 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ACTVOS()
2964 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == (PWR_SVMSR_VDDUSBRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDUSB()
2974 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == (PWR_SVMSR_VDDIO2RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDIO2()
2985 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == (PWR_SVMSR_VDDA1RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDA1()
2996 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == (PWR_SVMSR_VDDA2RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDA2()
3006 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATH()
3017 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPL()
3028 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPH()
3038 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
3048 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
3058 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
3068 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
3078 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
3088 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU6()
3098 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU7()
3108 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU8()
3118 WRITE_REG(PWR->SR, PWR_SR_CSSF); in LL_PWR_ClearFlag_STOP()
3128 WRITE_REG(PWR->SR, PWR_SR_CSSF); in LL_PWR_ClearFlag_SB()
3138 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); in LL_PWR_ClearFlag_WU1()
3148 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); in LL_PWR_ClearFlag_WU2()
3158 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); in LL_PWR_ClearFlag_WU3()
3168 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); in LL_PWR_ClearFlag_WU4()
3178 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); in LL_PWR_ClearFlag_WU5()
3188 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); in LL_PWR_ClearFlag_WU6()
3198 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); in LL_PWR_ClearFlag_WU7()
3208 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8); in LL_PWR_ClearFlag_WU8()
3218 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); in LL_PWR_ClearFlag_WU()
3235 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); in LL_PWR_EnableNSecurePrivilege()
3245 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); in LL_PWR_DisableNSecurePrivilege()
3255 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledNSecurePrivilege()
3266 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); in LL_PWR_EnableSecurePrivilege()
3276 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); in LL_PWR_DisableSecurePrivilege()
3287 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledSecurePrivilege()
3324 WRITE_REG(PWR->SECCFGR, SecureConfig); in LL_PWR_ConfigSecure()
3358 return (READ_REG(PWR->SECCFGR)); in LL_PWR_GetConfigSecure()