3385   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, tmp_resolution);  in LL_ADC_SetResolution()
3405   uint32_t tmp_resolution = (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));  in LL_ADC_GetResolution()
3432   MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_ALIGN, DataAlignment);  in LL_ADC_SetDataAlignment()
3447   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_ALIGN));  in LL_ADC_GetDataAlignment()
3505     MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_AUTDLY, LowPowerMode);  in LL_ADC_SetLowPowerMode()
3509     MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_WAIT, LowPowerMode);  in LL_ADC_SetLowPowerMode()
3564     return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_AUTDLY));  in LL_ADC_GetLowPowerMode()
3568     return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_WAIT));  in LL_ADC_GetLowPowerMode()
4085     MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);  in LL_ADC_REG_SetTriggerSource()
4089     MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC4_CFGR1_EXTSEL, TriggerSource);  in LL_ADC_REG_SetTriggerSource()
4134     __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);  in LL_ADC_REG_GetTriggerSource()
4149     __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC4_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);  in LL_ADC_REG_GetTriggerSource()
4177 …return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ?…  in LL_ADC_REG_IsTriggerSourceSWStart()
4197   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);  in LL_ADC_REG_SetTriggerEdge()
4212   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));  in LL_ADC_REG_GetTriggerEdge()
4382   MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD, Configurability);  in LL_ADC_REG_SetSequencerConfigurable()
4409   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD));  in LL_ADC_REG_GetSequencerConfigurable()
4589   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, SeqDiscont);  in LL_ADC_REG_SetSequencerDiscont()
4612   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM));  in LL_ADC_REG_GetSequencerDiscont()
4829   MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_SCANDIR, ScanDirection);  in LL_ADC_REG_SetSequencerScanDirection()
4847   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_SCANDIR));  in LL_ADC_REG_GetSequencerScanDirection()
5431   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);  in LL_ADC_REG_SetContinuousMode()
5448   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));  in LL_ADC_REG_GetContinuousMode()
5469   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMNGT, DataTransferMode);  in LL_ADC_REG_SetDataTransferMode()
5489   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT));  in LL_ADC_REG_GetDataTransferMode()
5527   MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG, DMATransfer);  in LL_ADC_REG_SetDMATransfer()
5560   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG));  in LL_ADC_REG_GetDMATransfer()
5585   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);  in LL_ADC_REG_SetOverrun()
5599   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));  in LL_ADC_REG_GetOverrun()
5823   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JDISCEN, SeqDiscont);  in LL_ADC_INJ_SetSequencerDiscont()
5838   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN));  in LL_ADC_INJ_GetSequencerDiscont()
5983   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JAUTO, TrigAuto);  in LL_ADC_INJ_SetTrigAuto()
5997   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO));  in LL_ADC_INJ_GetTrigAuto()
6739     preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);  in LL_ADC_SetAnalogWDMonitChannels()
6893     preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);  in LL_ADC_GetAnalogWDMonitChannels()