Lines Matching full:mode
57 uint32_t MemoryMode; /*!< It Specifies the memory mode.
140 used for memory-mapped mode).
146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
150 uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase.
154 …uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises numb…
159 uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase.
163 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
167 …uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
169 …uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of …
173 This field is only used for indirect mode.
175 uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase.
181 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. When SIOO mode enabled,
196 uint32_t LatencyMode; /*!< It configures the latency mode.
212 This field is only used for indirect mode.
214 In case of autopolling mode, this parameter can be
219 …uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of …
226 * @brief HAL XSPI Auto Polling mode configuration structure definition
245 * @brief HAL XSPI Memory Mapped mode configuration structure definition
338 …HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
369 /** @defgroup XSPI_MemoryMode XSPI Memory Mode
372 #define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */
373 #define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */
382 …L_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */
383 …L_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */
384 …L_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */
385 …L_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/
386 …L_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
387 …L_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */
441 /** @defgroup XSPI_ClockMode XSPI Clock Mode
531 …PE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
532 …PE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */
533 …PE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */
534 …PE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */
558 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode
581 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode
584 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
585 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for i…
590 /** @defgroup XSPI_AddressMode XSPI Address Mode
613 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode
616 #define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
617 #define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for …
622 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode
645 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode
648 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
649 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for …
654 /** @defgroup XSPI_DataMode XSPI Data Mode
669 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode
672 #define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
673 #define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for d…
678 /** @defgroup XSPI_DQSMode XSPI DQS Mode
687 /** @defgroup XSPI_SIOOMode XSPI SIOO Mode
705 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode
717 …e HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */
718 …e HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
723 /** @defgroup XSPI_MatchMode XSPI Match Mode
726 #define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between u…
727 #define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between un…
754 … XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode …
755 …SPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode …
816 …A_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operation…
972 /* XSPI indirect mode functions */
980 /* XSPI status flag polling mode functions */
985 /* XSPI memory-mapped mode functions */
993 /* XSPI indirect mode Callback functions */
1000 /* XSPI status flag polling mode functions */
1003 /* XSPI memory-mapped mode functions */
1092 #define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ argument
1093 ((MODE) == HAL_XSPI_DUAL_MEM))
1140 #define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ argument
1141 ((MODE) == HAL_XSPI_CLOCK_MODE_3))
1215 #define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ argument
1216 ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \
1217 ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \
1218 ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \
1219 ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES))
1226 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ argument
1227 ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
1229 #define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ argument
1230 ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \
1231 ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \
1232 ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \
1233 ((MODE) == HAL_XSPI_ADDRESS_8_LINES))
1240 #define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ argument
1241 ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE))
1243 #define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ argument
1244 ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \
1245 ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \
1246 ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \
1247 ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES))
1254 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ argument
1255 ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE))
1257 #define IS_OCTOSPI_DATA_MODE(MODE) (((MODE) == HAL_XSPI_DATA_NONE) || \ argument
1258 ((MODE) == HAL_XSPI_DATA_1_LINE) || \
1259 ((MODE) == HAL_XSPI_DATA_2_LINES) || \
1260 ((MODE) == HAL_XSPI_DATA_4_LINES) || \
1261 ((MODE) == HAL_XSPI_DATA_8_LINES))
1264 #define IS_HSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ argument
1265 (((MODE) == HAL_XSPI_DATA_NONE) || \
1266 ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1267 ((MODE) == HAL_XSPI_DATA_16_LINES)): \
1268 (((MODE) == HAL_XSPI_DATA_NONE) || \
1269 ((MODE) == HAL_XSPI_DATA_1_LINE) || \
1270 ((MODE) == HAL_XSPI_DATA_2_LINES) || \
1271 ((MODE) == HAL_XSPI_DATA_4_LINES) || \
1272 ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1273 ((MODE) == HAL_XSPI_DATA_16_LINES)))
1278 #define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ argument
1279 ((MODE) == HAL_XSPI_DATA_DTR_ENABLE))
1283 #define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ argument
1284 ((MODE) == HAL_XSPI_DQS_ENABLE))
1286 #define IS_XSPI_SIOO_MODE(MODE) (((MODE) == HAL_XSPI_SIOO_INST_EVERY_CMD) || \ argument
1287 ((MODE) == HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD))
1293 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ argument
1294 ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE))
1296 #define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ argument
1297 ((MODE) == HAL_XSPI_FIXED_LATENCY))
1302 #define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ argument
1303 ((MODE) == HAL_XSPI_MATCH_MODE_OR))
1305 #define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ argument
1306 ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE))
1312 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
1313 ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE))